Sudarshan Banerjee
List of Publications:
- S Banerjee, E Bozorgzadeh, N Dutt,
"Exploiting application data-parallelism on dynamically
reconfigurable architectures: placement and architectural
considerations", [ACCEPTED] IEEE Trans on VLSI
- M Kim, S Banerjee, N Dutt, N Venkatasubramaniam, "Energy-aware Cosynthesis of Real Time Multimedia Applications on MPSoCs", ACM Trans on Embedded Computing Systems, Vol 7(2), Feb 2008, pp 1-19
- A H Gholamipour, E Bozorgzadeh, S Banerjee, "Energy-Aware Co-processor Selection for Embedded Processors on FPGAs", IEEE ICCD, Lake Tahoe (California), Oct 2007
- S Banerjee, E Bozorgzadeh, J Noguera, N Dutt, "Selective Bandwidth and Resource Management in Scheduling for Dynamically Reconfigurable Architectures", DAC, San Diego (California), June 2007, pp 771-776
- S Banerjee, E Bozorgzadeh, J Noguera, N Dutt, "Minimizing
peak power for application chains on architectures with partial dynamic
reconfiguration", IEEE FPT, Bangkok, Dec 2006,
pp 273-276
- S Banerjee, E Bozorgzadeh, N Dutt, "Integrating
physical
constraints in HW-SW partitioning for architectures with partial
dynamic
reconfiguration", IEEE Trans on VLSI, Vol 14(11), Nov
2006, pp 1189-1202
- M Kim, S Banerjee, N Dutt, N Venkatasubramaniam, "Design
Space
Exploration of Realtime Multimedia MPSoCs with Heterogeneous
Scheduling
Policies", ACM/IEEE CODES+ISSS, Seoul, Oct 2006, pp 16-21
- J Augustine, S Banerjee, S Irani, "Strip Packing with
Precedence
Constraints and Strip Packing with Release Times", ACM SPAA,
Cambridge (Massachusetts), Aug 2006, pp 180-189
- P Biswas, S Banerjee, N Dutt, L Pozzi, P Ienne, "ISEGEN:
An
Iterative-Improvement-based ISE Generation Technique for Fast
Customization
of Processors", IEEE Trans on VLSI, Vol 14(7), July 2006, pp
754-762
- S Banerjee, E Bozorgzadeh, N Dutt, "PARLGRAN: Parallelism
granularity
selection for scheduling task chains on dynamically reconfigurable
architectures", ASP-DAC, Yokohama (Japan), Jan 2006, pp
491-496
- P Biswas, S Banerjee, N Dutt, L Pozzi, P Ienne,
"Performance and Energy Benefits of Instruction Set Extensions in an
FPGA Soft Core", VLSI Design,
Hyderabad (India), Jan 2006, pp 651-656
- S Banerjee, E Bozorgzadeh, N Dutt, "Physically-aware HW-SW
Partitioning
for reconfigurable architectures with partial dynamic reconfiguration",
DAC, Anaheim (California), June 2005, pp 335-340
- S Banerjee, E Bozorgzadeh, N Dutt, "Considering runtime
reconfiguration
overhead in Task Graph Transformations for dynamically reconfigurable
architectures",
IEEE FCCM, Napa (California), April 2005, pp 273-274
- P Biswas, S Banerjee, N Dutt, L Pozzi, P Ienne, "ISEGEN:
Generation
of High-Quality Instruction Set Extensions by Iterative Improvement",
DATE,
Munich, Mar 2005, pp 1246-1251
- S Banerjee, N Dutt, "Efficient Search Space Exploration
for
HW-SW Partitioning", ACM/IEEE CODES+ISSS, Stockholm,
Sept 2004,
pp 122-127
- P Biswas, S Banerjee, N Dutt, L Pozzi, P Ienne, "Fast
Automated
Generation of High-Quality Instruction Set Extensions for Processor
Customization",
Workshop on Application Specific Processors (WASP),
Stockholm,
Sep 2004
- S Banerjee, N Dutt, "FIFO Power Optimization for On-chip
Networks",
ACM Great Lakes Symposium on VLSI (GLSVLSI), Boston,
April
2004, pp 187-191
- S Banerjee, S Saxena, "Parallel Algorithms for Finding the
Most
Vital Edge in Weighted Graphs", Jrnl of Parallel
and Distrib Computing, Vol 46(1), 1997, pp 101-104
- S Banerjee, R K Ghosh, A P K Reddy, "Parallel Algorithm
for
Shortest Pairs of Edge-Disjoint Paths", Jrnl of Parallel
and Distrib Computing, Vol 33(2), 1996, pp 165-171