System Design Using IC Cores; Design, Test and Sign-Off

Prelude:

Core-based designs are becoming common due to increased complexity of systems and a drive to reuse previous design efforts. Core-based designs represent a special challenge in almost all aspects of IC/System design because of the requirements to integrate diverse components with little or no modifications to individual block or core cells. Tools and methodologies are needed for design and validation. This tutorial is devoted to understanding of the issues related to core design, test and use.

Presenters:

Tutorial Outline and Slides

Important Notice:

Please read the notice at the bottom of this document. You may browse freely the material in this section and copy for personal use provided appropriate attributation to the document source is made. No part of the material here can be retrieved, copied or distributed for profit or commercial reasons without prior written permission from the author of this page. 

Welcome (activex) 


Introduction to Embedded Cores (activex) 
        - What are cores?
        - Where to use cores?
        - Who are the core players?


Design for Test of Core-Based Systems (activex) 
        - Testing problem of cores and core-based designs
        - Designing cores for testability
        - Some proposed methodologies - BIST, scan, and boundary scan -
          their pros and cons


System Validation (activex) 
        - Validation strategies
        - Simulation basics
        - Co-Simulation
        - Emulation


Reusable Components/Blocks: User Experiences (activex) 


The Future (activex) 
        - Cores as a vehicle for IP-content: CAD tool requirements

Core BookMarks:

IP Suppliers

Summary list can be found for: Hard cores Soft cores and DSP guides.

Services

Magazines

Standards Organizations

Articles

Miscellaneous

i-Logix Inc. - Systems Design Automation Tools - CAD ASIC VHDL
Design Automation Cafe
Embedded Systems Internet -- Resource Page
Design SuperCon97
Motorola Defines ColdFire Core Again
Verilog & EDA Web Page
VHDL Tutorial
Networked Computer Science Technical Reports Library
Routing/Interconnection Network Research Sites
Stanford University CS Electronic and Technical Reports Library
Embedded Systems Conference HomePage
TechWeb --The Technology Super Site
CPU Info Center
IEEE Cores Requirements Survey
DesignCon98

Bibliography: Test Issues 

 "Test Methodolgy for Embedded Cores which Protects Intellectual Property", K.
De, IEEE VLSI Test Symposium, 1997, pp. 1-6.

 "Partial Isolation Rings for Testing Embedded Cores", IEEE VLSI Test
Symposium, 1997, pp. 7-13.

 "Hierarchical Test Assembly for Macro Based VLSI Design," J. Leenstra and
L. Spaanenburg, International Test Conference, 1990, pp 520-529.

 "A Framework and Method for Hierarchical Test generation," J. D. Calhoun and
F. Brglez, IEEE Transactions on Computer-Aided Design, pp 45-67, January 1992.

 "Macro Testability; The Result of Production Device Application, F. Bouwan
et. al., International Test Conference 1992, pp 232-241

 "A Hierarchical Test Pattern Generation System Based on High-Level
Primitives," T. M. Sarfert et al, IEEE Transaction on Computer-Aided Design,
pp 34-44, January 1992.

 "Hierarchical Test Generation under Intensive Global Functional Constraints,"
J. Lee and J. H. Patel, Design Automation Conference, 1992, pp 261-266.

 "Hierarchical Test Generation Using Precomputed Tests for Modules,"
B. T. Murray and J. P. Hayes, International Test Conference, 1988, pp 221-229.

 "MATEG: A Hierarchical Test Generator for Module-Based Circuits,"
D. R. Chiang and Michal Cutler, Fifth Annual IEEE ASIC Conference and Exhibit,
1992, pp 491-494.  

 "Hierarchical Test Generation: Where We Are, And Where
We Should Be Going," J. R. Armstrong, European Design Automation Conference,
1993, pp 434-439.  

 "Explicit Fault Modeling and Hierarchical Test Pattern
Generation in the KARATE System," G Alfs, R. Hartenstein and A. Wodtko,
Microprocessor & Microprogramming, August 1989, pp 675-680.  


"Managing ASIC IP Throughout Product Life Cycles", D. Crate,  On-Chip
System Design Conference, Design Supercon, 1997, pp S231-1 through S231-14.

"Design Envrionment for System-on-a-Chip", C. Cherichetti et al, On-Chip
System Design Conference, Design Supercon, 1997, pp S312-1 through S312-25.

"Business and Legal Challenges in the Emerging Systems on a Chip Market",
P. Lippe, The Intellectual Property in Electronics Conference and
Exhibition, 1997, pp 82-100.

Bibliography: Standards and IP Issues 

 "VSI Alliance Architecture Document", version 1.0, 1997.

 "VSI Alliance Roadmap", version 1.0, 1997.

Annotated Bibliography: Research Perspective

Important Notice:

This on-line material is being provided in the interest of rapid dissemination of information related to the tutorial presented at DAC 1997. Some or all of the material here may be covered by copyright owned by the respective authors. You may browse the material at your convenience as you would in a public library. Permission is also granted to make a hard copy for personal use without fee provided that the copied material clearly indicates the author and source of the material and any original copyright notations are unaltered. Retrieval, copy, or distribution of any material herein for profit or any commerical advantage may violate the copyright protection law and requires prior written permission of the copyright owners.
rgupta@ics.uci.edu

Last updated: Thu May 15 17:40:31 PDT 1997