Conferences

C1 D.D. Gajski, N.D. Dutt and B.M. Pangrle, “Silicon Compilation: A Tutorial,” Proceedings of the IEEE Custom Integrated Circuits Conference, Rochester, NY, May 1986.

 
C2 N.D. Dutt and D.D. Gajski, “Designer Controlled Behavioral Synthesis,” Proceedings of the ACM/IEEE 26th Design Automation Conference, Las Vegas, NV, June 1989, pp. 754-757.

 
C3 N.D. Dutt and D.D. Gajski, “EXEL: A Language for Interactive Behavioral Synthesis,” Proceedings of the IFIP/ACM Ninth International Symposium on Computer Hardware Description Languages (CHDL 89), Washington DC, June 1989, pp. 3-17. BEST PAPER AWARD

 
C4 N.D. Dutt, “LEGEND: A Language for Generic Component Library Description,” Proceedings of the IEEE 1990 International Conference on Computer Languages, March 1990, pp. 198-207.

 
C5 N.D. Dutt, T. Hadley and D.D. Gajski, “An Intermediate Representation for Behavioral Synthesis,” Proceedings of the ACM/IEEE 27th Design Automation Conference, June 1990, pp. 14-19. 

 
C6 N.D. Dutt, “Generic Component Library Characterization for High Level Synthesis,” VLSI Design 91, The Fourth CSI/IEEE International Symposium on VLSI Design, New Delhi, India, January 1991, pp. 5-10.

 
C7 N.D. Dutt, J. Cho and T. Hadley, “A User Interface for Behavioral VHDL Modeling,” Proceedings of the IFIP/ACM Tenth International Symposium on Computer Hardware Description Languages (CHDL 91), Marseille, France, April 1991, pp. 375-390. BEST PAPER AWARD

 
C8 N.D. Dutt and J.R. Kipps, “Bridging High Level Synthesis to RTL Technology Libraries,” Proceedings of the ACM/IEEE 28th Design Automation Conference, June 1991, pp. 526-529.

 
C9 H. Wang, N.D. Dutt and A. Nicolau, “Harmonic Scheduling of Linear Recurrences in Digital Filter Design,” Proceedings of the 1st European Design Automation Conference, September 1992, pp. 396-401.

 
C10 D.D. Gajski and N.D. Dutt, “Benchmarking and the Art of Synthesis Tool Comparison,” Proceedings IFIP Workshop on Control-Dominated Synthesis from a Register-Transfer Level Description, September 1992, pp. 439-453. (Invited Paper).

 
C11 R. Ang and N.D. Dutt, “Equivalent Design Representations and Transformations for Interactive Rescheduling,” Proceedings of International Conference on Computer-Aided Design (ICCAD-92), November 1992, pp. 332-335.

 
C12 A. Capitanio, N.D. Dutt and A. Nicolau, “Partitioned Register Files for VLIWs: A Preliminary Analysis of Tradeoffs,” MICRO-25: The 25th Annual International Symposium on Microarchitecture, Portland, OR, December 1992.

 
C13 H. Wang, N.D. Dutt and A. Nicolau, “Optimal Scheduling of Recursive Digital Filters with Resource Constraints,” Proceedings of 1992 International Computer Symposium, Taiwan, December 1992.

 
C14 H. Wang, N.D. Dutt and A. Nicolau, “Harmonic Scheduling: A Technique for Scheduling Beyond Loop-Carried Dependencies,” Proceedings of VLSI Design 1993, January 1993, pp. 198-201.

 
C15 R. Ang and N.D. Dutt, “A Representation for the Binding of RT-Component Functionality to HDL Behavior,” Proceedings of the IFIP/ACM Eleventh International Conference on Hardware Description Languages (CHDL 93), Ottawa, Canada, April 1993, pp. 263-280.

 
C16 H. Wang, N.D. Dutt, A. Nicolau and K.S. Siu, “High-Level Synthesis of Scalable Architectures for IIR Filters Using Multichip Modules,” Proceedings of the ACM/IEEE 30th Design Automation Conference, June 1993, pp. 336-342.

 
C17 H. Wang, N.D. Dutt and A. Nicolau, “MCM-Based Architectural Synthesis of IIR Digital Filters,” Proceedings of the Conference on CAD/Graphics 93, Beijing, China, 1993.

 
C18 H. Wang, N.D. Dutt and A. Nicolau, “Regular Schedules for Scalable Design of IIR Filters,” Proceedings of the 2nd European Design Automation Conference, September 1993.

 
C19 C. Ramachandran, P.K. Jha, F. Kurdahi and N.D. Dutt, “Towards More Realistic Physical Design Models for High-Level Synthesis,” Proceedings of ICVC-93, November 1993.

 
C20 N.D. Dutt and P.K. Jha, “RT Component Sets for High-Level Design Applications,” The 1st IEEE Asia Pacific Conference on Hardware Description Languages, Standards and Applications, Brisbane, Australia, December 1993, pp. 43-54.

 
C21 D. Kolson, N.D. Dutt and A. Nicolau, “Ultra-Fine Grain Template Driven Synthesis,” Proceedings of VLSI Design 1994, January 1994, pp. 25-28.

 
C22 P.K. Jha and N.D. Dutt, “Rapid Technology Projection for High-Level Synthesis,” Proceedings of VLSI Design 1994, January 1994, pp. 155-158.

 
C23 P.K. Jha, C. Ramachandran, N.D. Dutt and F. Kurdahi, “An Empirical Study in the Effects of Physical Design in High-Level Synthesis,” Proceedings of VLSI Design 1994, January 1994, pp. 11-16.

 
C24 R. Ang and N.D. Dutt, “An Algorithm for the Allocation of Functional Units from Realistic Libraries,” Proceedings of the Seventh International Symposium on High-Level Synthesis (HLSS94), May 1994, pp. 164-169.

 
C25 S. Parameswaran, P.K. Jha and N.D. Dutt, “Resynthesizing Controllers for Minimum Execution Time,” The 2nd Asia Pacific Conference on Hardware Description Languages, Toyohashi, Japan, October 1994.

 
C26 D. Kolson, N.D. Dutt and A. Nicolau, “Minimization of Memory Traffic in High-Level Synthesis,” Proceedings of the 31st ACM/IEEE Design Automation Conference, June 1994, pp. 149-154.

 
C27 A. Capitanio, N.D. Dutt and A. Nicolau, “Allocation of Multiple Register Files for VLIW Architectures,” Proceedings of the 1994 International Conference on Parallel Processing, August 1994.

 
C28 D. Kolson, A. Nicolau and N.D. Dutt, “Integrating Program Transformations in the Memory-Based Synthesis of Image and Video Algorithms,” Proceedings of the 1994 International Conference on Computer-Aided Design (ICCAD-94), November 1994, pp. 27-30. 

 
C29 S. Oum, F. Kurdahi and N.D. Dutt, “Comprehensive Lower Bound Estimation from Behavioral Descriptions,”  Proceedings of the 1994 International Conference on Computer-Aided Design (ICCAD-94), November 1994, pp. 182‑187. 

 
C30 P. Conradi and N.D. Dutt, “A Compound Information Model for High-Level Synthesis,” Proceedings of the 4th International IFIP 10.5 Working Conference on Electronic Design Automation Frameworks (EDAF-94), December 1994, pp. 189-198.

 
C31 F. Onion,  A. Nicolau and N.D. Dutt, “Incorporating Compiler Feedback into the Design of ASIPs,” Proceedings of the 1995 European Design and Test Conference (ED&TC 1995), March 1995, pp. 508-513. 

 
C32 P.K. Jha and N.D. Dutt, “Design Reuse through High-Level Library Mapping,” Proceedings of the 1995 European Design and Test Conference (ED&TC 1995), March 1995, pp. 345-350. 

 
C33 S. Parameswaran, P.K. Jha and N.D. Dutt, “Reclocking for High-Level Synthesis,” The First Asia-Pacific Design Automation Conference (ASPDAC-95), Tokyo, Japan, August 1995.

 
C34 D. Kolson, A. Nicolau, N.D. Dutt and K. Kennedy, “Optimal Register Assignment to Loops for Embedded Code Generation,” Proceedings of the 1995 International Symposium on System Synthesis, September 1995. 

 
C35 F. Kurdahi, S. Ohm, N.D. Dutt and M. Xu, “A Comprehensive Estimation Technique for High-Level Synthesis,”  Proceedings of the 1995 International Symposium on System Synthesis, September 1995, pp. 122-127.

 
C36 P.R. Panda and N.D. Dutt, “The 1995 High-Level Synthesis Design Repository,” Proceedings of the 1995 International Symposium on System Synthesis, September 1995, pp. 170-174. Invited Paper.  

 
C37 P.R. Panda and N.D. Dutt, “Reducing Address Bus Transitions for Low Power Memory Mapping,” Proceedings of the 1996 European Design & Test Conference (ED&TC), March 1996.

 
C38 D. Kolson, A. Nicolau, N.D. Dutt and K. Kennedy, “A Method for Register Allocation to Loops in Multiple Register File Architectures,” Proceedings of the 1996 International Conference on Parallel Processing (IPPS’96), April 1996.  

 
C39 T. Hironaka, A. Halambi, A. Nicolau and N.D. Dutt, “Speculative Execution by Compiler Supported Hardware Branch Prediction,” Proceedings of 1996 IPSJ ARC, Proceedings of CPSY’96, Ritsumeikan, Japan, May 1996.  

 
C40 P.R. Panda and N.D. Dutt, “Low-Power Mapping of Behavioral Arrays to Multiple Memories,” Proceedings of the 1996 International Symposium on Low Power Electronics and Design, August 1996

 
C41 P.R. Panda, N.D. Dutt and A. Nicolau, “Memory Organization for Improved Data Cache Performance in Embedded Processors,” Proceedings of the 1996 International Symposium on System Synthesis, November 1996.

 
C42 P.R. Panda and N.D. Dutt, “Behavioral Array Mapping into Multiport Memories Targeting Low Power,” Proceedings of VLSI Design 1997, January 1997.

 
C43 P.K. Jha and N.D. Dutt, “Library Mapping for Memories,” Proceedings of the 1997 European Design and Test Conference (ED&TC 1997), March 1997. 

 
C44 P.R. Panda, N.D. Dutt and A. Nicolau, “Efficient Utilization of Scratch-Pad Memory in Embedded Processor Applications,” Proceedings of the 1997 European Design and Test Conference (ED&TC 1997), March 1997.

 
C45 P. Panda, H. Nakamura, N.D. Dutt and A. Nicolau, “Improving Cache Performance through Tiling and Data Alignment,” Proceedings of the 4th International Symposium on Solving Irregularly Structured Problems in Parallel,”  June 11-13, 1997.  (Invited Paper).

 
C46 P.R. Panda, N.D. Dutt and A. Nicolau, “Architectural Exploration and Optimization of Local Memory in Embedded Systems,” Proceedings of the 1997 International Symposium on System Synthesis (ISSS’97), September 1997.

 
C47 N.D. Dutt, “Memory Organization and Exploration for Embedded Systems-on-Silicon,” Proceedings of the 1997 International Conference on VLSI and CAD (ICVC’97), October 1997 (Invited Paper).

 
C48 P.R. Panda, H. Nakamura, N.D. Dutt and A. Nicolau, “Data Alignment for Improved Data Cache Performance,”  Proceedings of the International Conference on Computer Design,  Austin, TX, October, 1997

 
C49 N.D. Dutt, S. Malik, L. Augusteijn, B. Fu, A. Nicolau and C. Polychronopoulos, “If Software is King for Systems-on-Silicon, What’s New in Compilers?,” Proceedings of the International Conference on Computer Design, Austin, TX, October, 1997.

 
C50 P.R. Panda, N.D. Dutt and A. Nicolau, “Exploiting Off-Chip Memory Access Modes in High-Level Synthesis,” Proceedings of the 1997 International Conference on Computer-Aided Design (ICCAD-97), November 1997. 

 
C51 P.R. Panda, N.D. Dutt and A. Nicolau, “Data Cache Sizing for Embedded Processor Applications,” Proceedings of the 1998 Design, Automation and Test in Europe Conference (DATE-98), February 1998. 

 
C52 P. Grün, F. Balasa and N.D. Dutt, “Memory Size Estimation for Multimedia Applications,” Proceedings of the 6th International Workshop on Hardware/Software Co-Design (CODES/CASHE’98), Seattle, WA, March 15‑18, 1998. 

 
C53 D. Kolson, A. Nicolau and N.D. Dutt, “Copy Elimination for Parallelizing Compilers,” Proceedings of LCPC’98: The 11th International Workshop on Languages and Compilers for Parallel Computing, August 1998.

 
C54 A. Khare, P.R. Panda, N.D. Dutt and A. Nicolau, “High-Level Synthesis with Synchronous DRAMs,” Proceedings of SASIMI’98: The Eighth Workshop on Synthesis and System Integration of Mixed Technologies, October 1998. 

 
C55 N.D. Dutt and A. Nicolau, “Supporting Architectural Exploration of Embedded Systems-on-Chip through Software Toolkit Generation,” Proceedings of SASIMI’98: The Eighth Workshop on Synthesis and System Integration of Mixed Technologies, October 1998 (Invited Paper).

 
C56 A. Halambi, P. Grün, V. Ganesh, A. Khare, N.D. Dutt and A. Nicolau, “EXPRESSION: A Language for Architectural Exploration through Compiler/Simulator Retargetability,” Proceedings of the 1999 Design, Automation and  Test in Europe Conference (DATE-99), March 1999. 

 
C57 A. Khare, N. Savoiu, A. Halambi, P. Grün, N.D. Dutt and A. Nicolau, “V-SAT: A Visual Specification and Analysis Tool for System-on-Chip Exploration,” Proceedings of the 1999 Digital System Workshop, Euromicro’99, September 1999. 

 
C58 H. Tomiyama, A. Halambi, P. Grün, N.D. Dutt and A. Nicolau, "Architectural Description Languages for Systems-on-Chip Design," Proceedings of the 1999 Asia Pacific Conference on Chip Design Languages (APChDL'99), October 1999.

 
C59 A. Halambi, H. Tomiyama, P. Grün, N.D. Dutt and A. Nicolau, “Automatic Software Toolkit Generation for Embedded Systems-on-Chip,” Proceedings of the 1999 International Conference on VLSI and CAD (ICVC’99),  October 1999 (Invited Paper).

 
C60  H. Tomiyama, A. Halambi, P. Grün, N.D. Dutt and A. Nicolau, "Modeling and Verification of Processor Pipelines in SOC Design Exploration,”  Proceedings of the IEEE International High Level Design Validationa and Test Workshop (HLDVT'99), November 1999.

 
C61 P. Grün, A. Halambi, N.D. Dutt and A. Nicolau, “RTGEN: An Algorithm for Automatic Generation of Reservation Tables from Architectural Descriptions,” Proceedings of the 1999 International Symposium on System Synthesis (ISSS‑99), November 1999.  

 
C62 F. Catthoor, N. Dutt and C. Kozyrakis, “Hot Topic Session: How to Solve the Current Memory Access and Data Transfer Bottlenecks: at the Processor Architecture or at the Compiler Level?,” Proceedings of the 2000 Design, Automation and  Test in Europe Conference (DATE-2000), March 2000.   (Invited Paper)

 
C63 A. Halambi, R. Cornea, P. Grun, N. Dutt and A. Nicolau, “Architecture Exploration of Parameterizable EPIC SOC Architectures,” Proceedings of the 2000 Design, Automation and  Test in Europe Conference, (DATE-2000), March 2000.   (Poster Paper)

 
C64 A. Datta, S. Choudhury, A. Basu, H. Tomiyama, and N. Dutt, “Task Layout Generation to Minimize Cache Miss Penalty for Preemptive Real Time Tasks: An ILP Approach,”Proc. of 9th Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI 2000), pp. 202--208, Kyoto, Japan, April 2000.

 
C65 H. Tomiyama and N. Dutt, “Program Path Analysis to Bound Cache-Related Preemption Delay in Preemptive Real-Time Systems,” Proc. of the 8th International Workshop on Hardware/Software Codesign (CODES2000), pp. 67--71, San Diego, CA, USA, May 2000.

 
C66 P. Grun,  N. Dutt and A. Nicolau, “Memory aware compilation through accurate timing extraction,” Proceedings of the 37th Design Automation Conference (DAC-2000), June 2000.

 
C67 L. Nachtergaele, V. Tiwari and N. Dutt, “System and Architecture-level Power Reduction of Microprocessor-based Communication and Multi-media Applications,” embedded tutorial in Proceedings of the International Conference on Computer-Aided Design 2000 (ICCAD-2000), November 2000.

 
C68 P. Grun, N. Dutt and A. Nicolau, “MIST: An Algorithm for Memory Miss Traffic Management,” Proceedings of the International Conference on Computer-Aided Design 2000 (ICCAD-2000), November 2000.

 
C69 H. Tomiyama, T. Yoshino  and N. Dutt, “Verification of In-Order Execution in Processor Pipelines,” Proceedings of the IEEE International High Level Design Validation and Test Workshop (HLDVT'00), November 2000.

 
C70 P. Mishra, P. Grun, N. Dutt and A. Nicolau, “Processor-Memory Co-Exploration,” Proceedings of the VLSI Design 2001 Conference, January 2001.

 
C71 A. Datta, S. Choudhury, A. Basu, H. Tomiyama, and N. Dutt, “Satisfying Timing Constraints of Preemptive Real-Time Tasks through Task Layout Techniques,” Proceedings of the VLSI Design 2001 Conference, January 2001.

 
C72 N. Dutt, A. Nicolau, H. Tomiyama and A. Halambi, “New Directions in Compiler Technology for Embedded Systems,” Proc. Asia and South Pacific Design Automation Conference (ASP-DAC 2001), Yokohama, Japan, January 2001.

 
C73 A. Azevedo, R. Cornea, I. Issenin, R. Gupta, A. Nicolau and N. Dutt, “Architectural and Compiler Strategies for Dynamic Power Management in the COPPER Project,” Proceedings of the IWIA, January 2001.

 
C74 P. Grun, N. Dutt and A. Nicolau, “Access Pattern based Local Memory Customization for Low Power Embedded Systems,” Proceedings of the 2001 Design, Automation and  Test in Europe Conference (DATE-2001), March 2001.

 
C75 S. Gupta, N. Savoiu, S. Kim, N.D. Dutt, R.K. Gupta and A. Nicolau, “Speculation Techniques for High-Level Synthesis of Control Intensive Designs,” Proceedings of the 38th DAC, June 2001.

 
C76 M. Mamidipaka, D. Hirschberg, N.D. Dutt, “Low Power Address Encoding using Self-Organizing Lists,” Proceedings of ISLPED-01, August 2001.

 
C77 P. Grun,  N. Dutt and A. Nicolau, “APEX: Access Pattern Based Memory Exploration,” Proceedings of the 2001 International Symposium on System Synthesis (ISSS-2001), pp. 25-32,  October 2001.

 
C78 S. Gupta, N. Savoiu, N.D. Dutt, R.K. Gupta and A. Nicolau, “Conditional Speculation and its Effects on Performance and Area for High-Level Synthesis,” Proceedings of the 2001 International Symposium on System Synthesis (ISSS-2001), pp. 171-176, October 2001.

 
C79 P. Mishra, J. Astrom, N.D. Dutt, A. Nicolau, “Functional Abstraction Driven Design Space Exploration of Heterogeneous Programmable Architectures,” Proceedings of the 2001 International Symposium on System Synthesis (ISSS-2001), pp. 256-261,  October 2001.

 
C80 P. Mishra, F. Rousseau, N. Dutt, A. Nicolau, “Architecture Description Language Driven Design Space Exploration in the Presence of Coprocessors,” Proceedings of the 10th Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI 2001), October 2001.

 
C81 P. Mishra, N. Dutt, A. Nicolau, “Automatic Validation of Pipeline Specifications,” Proceedings of the IEEE International High Level Design Validation and Test  Workshop (HLDVT'01), pp. 9-13, November 2001.

 
C82 P. Mishra, H. Tomiyama, A. Halambi, P. Grun, N. Dutt, A. Nicolau, “Automatic Modeling and Validation of Pipeline Specifications driven by an Architecture Description Language,” Proceedings of ASPDAC-2002/VLSI Design 2002, pp. 458-463, January 2002.

 
C83 P. Mishra, H. Tomiyama, N.D. Dutt and A. Nicolau, “Automatic Verification of In-order Execution in Microprocessors with Fragmented Pipeleines and Multicycle Functional Units,” Proceedings of the 2002 Design, Automation and Test in Europe Conference (DATE-2002),  pp. 36-43, March 2002.

 
C84 A. Azevedo, I. Issenin, R. Cornea, R. Gupta, N. Dutt, A. Veidenbaum and A. Nicolau, “Profile-based Dynamic Voltage Scheduling using Program Checkpoints,” Proceedings of the 2002 Design, Automation and  Test in Europe Conference (DATE-2002), pp. 168-175, March 2002.

 
C85 A. Halambi, A. Shrivastava, P. Biswas, N. Dutt, and A. Nicolau, “An Efficient Compiler Technique for Code Size Reduction using Reduced Bit-width ISAs,” Proceedings of the 2002 Design, Automation and  Test in Europe Conference (DATE-2002), pp. 402-408, March 2002

 
C86 P. Grün, N. Dutt, and A. Nicolau, “Memory System Connectivity Exploration,” Proceedings of the 2002 Design, Automation and  Test in Europe Conference (DATE-2002), pp. 894-901, March 2002

 
C87 S. Gupta, N. Savoiu, N.D. Dutt, R.K. Gupta, A. Nicolau, T. Kam, M. Kishinevsky, S. Rotem, “Coordinated Transformations For High-Level Synthesis Of High Performance Microprocessor Blocks,” Proceedings of the 39th DAC, June 2002,  pp, 898-903.

 
C88 A. Halambi, A. Shrivastava, P. Biswas, N. Dutt, and A. Nicolau, “A Design Space Exploration Framework for Reduced Bit-width Instruction Set Architecture (rISA) Design,” Proceedings of the 2002 International Symposium on System Synthesis (ISSS-2002), pp. 120-125, Kyoto, Japan, October 2002.

 
C89 M. Mamidipaka, N. Dutt, and D. Hirschberg, “Efficient Power Reduction Techniques for Time Multiplexed Address Buses,”   Proceedings of the 2002 International Symposium on System Synthesis (ISSS-2002), pp. 207-212, Kyoto, Japan, October 2002.

 
C90 S. Gupta, N. Savoiu, N.D. Dutt, R.K. Gupta and A. Nicolau, “Dynamic Common Sub-Expression Elimination during Scheduling in High-Level Synthesis,” Proceedings of the 2002 International Symposium on System Synthesis (ISSS-2002), pp. 261-266, Kyoto, Japan, October 2002.

 
C91 P. Mishra and N. Dutt,  “Automatic Functional Test Program Generation for Pipelined Processors using Model Checking,” Proceedings of the High Level Design Validation and Test (HLDVT), Cannes, France, , pp. 99-103, October, 2002.

 
C92 J. Lee, K. Choi and N.D. Dutt, “Mapping Loops on Coarse-Grain Reconfigurable Architectures using Memory Operation Sharing,”  Proceedings of the 1st Workshop on Application Specific Processors (WASP-1), Istanbul, Turkey, November 2002.

 
C93 J. Lee, K. Choi and N.D. Dutt, “Efficient Instruction Encoding for Automatic Instruction Set Design of Configurable ASIPs,” Proceedings of the International Conference on Computer-Aided Design 2002 (ICCAD-2002), pp. 649-654, November 2002.

 
C94 P.R. Panda and N.D. Dutt, “Memory Architecture Exploration for Embedded Systems,” Proceedings of the 9th International Conference on High Performance Computing (HiPC02), December 2002.

 
C95 M. Mamidipaka, K. Khouri and N.D. Dutt, “A Methodology for Accurate Modeling of Energy Dissipation in Array Structures,” Proceedings of VLSI Design 2003, January 2003.

 
C96 S. Gupta, N.D. Dutt, R. Gupta and A. Nicolau, “SPARK: A High-Level Synthesis Framework for Applying Parallelizing Compiler Transformations,” Proceedings of VLSI Design 2003, January 2003. (BEST PAPER AWARD) 

 
C97 M. Mamidipaka and N.D. Dutt, “On-chip Stack based Memory Organization for Low Power Embedded Architectures,” Proceedings of the 2003 Conference on Design Automation and Test in Europe (DATE-2003), Germany (2003).

 
C98 S. Gupta, N.D. Dutt,  R. Gupta and A. Nicolau, “Dynamic Conditional Branch Balancing during the High-Level Synthesis of Control-Intensive Design,” Proceedings of the 2003 Conference on Design, Automation and Test in Europe (DATE 2003), March 2003.    

 
C99 R. Cornea, N. D. Dutt, R. K. Gupta, I. Krüger, A. Nicolau, D. Schmidt, S.K. Shukla, “FORGE: A Framework for Optimization of Distributed Embedded Systems Software,”  Proceedings of the 17th IEEE/ACM  International Parallel and Distributed Processing Symposium (IPDPS 2003) : 208

 
C100 M. Reshadi, P. Mishra, and N.D. Dutt, “Instruction Set Compiled Simulation: A Technique for Fast and Flexible Instruction Set Simulation,” Proceedings of Design Automation Conference 2003 (DAC 2003) , pages xx-yy, Anaheim, USA, June 2003.

 
C101 J. Lee, K. Choi, and N.D. Dutt, “An Algorithm For Mapping Loops Onto Coarse-Grained Reconfigurable Architectures,” Proceedings of  the ACM 2003 Languages, Compilers, and Tools for Embedded Systems (LCTES-03), pp. 183-188,  San Diego, USA,  June 2003.

 
C102 P. Mishra, A. Kejariwal, and N.D. Dutt, “Rapid Exploration of Pipelined Processors through Automatic Generation of RTL Models,” Proceedings of the IEEE 2003 Rapid Systems Prototyping Workshop (RSP-2003), pp. 226-232, San Diego, USA,  June 2003.

 
C103 J. Lee, K. Choi, and N.D. Dutt, “Evaluating Memory Architectures for Media Applications on Coarse-Grained Reconfigurable Architectures,” Proceedings of IEEE 14th International Conference on Application-specific Systems, Architectures and Processors (ASAP-2003), The Hague, Holland, June 2003.

 
C104 J. Lee, K. Choi, and N.D. Dutt, “Energy-Efficient Instruction Set Synthesis for Application Specific Processors,” Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED-2003), Seoul, Korea, pp. 330-333,  August 2003.

 
C105 P. Mishra and N.D. Dutt, “A Framework for Validation of Programmable Embedded Systems driven by an Architecture Description Language,”  Proceedings of the 4th IEEE International Workshop on Microprocessor Testing and Verification (MTV-2003), Austin, TX, June 2003.

 
C106 M. Reshadi, N. Bansal, P. Mishra, and N.D. Dutt, "An Efficient Retargetable Framework for Instruction-Set Simulation", Proceedings of the International Symposium on Hardware/Software Codesign and System Synthesis (CODES+ISSS ),pp. 13-18, Newport Beach, California, USA, October 1-3, 2003.(BEST PAPER AWARD)

 
C107 M. Luthra, S. Gupta, N.D. Dutt, R.K. Gupta, A. Nicolau, Interface Synthesis using Memory Mapping for an FPGA Platform,” International Conference on Computer Design (ICCD), October 2003.

 
C108 M. Reshadi and N.D. Dutt, "Reducing Compilation Time Overhead in Compiled Simulators,” International Conference on Computer Design (ICCD), October 2003.

 
C109 P. Biswas and N.D. Dutt, “Reducing Code Size for Heterogeneous-Connectivity-Based VLIW DSPs through Synthesis of Instruction Set Extensions,” Proc. Of the 2003 International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES-2003), Oct 30-Nov 1, 2003, San Jose, CA.

 
C110 S. Mohapatra, R. Cornea,  N.D. Dutt, A. Nicolau, and N. Venkatasubramanian, " Integrated Power Management for Video Streaming to Mobile Handheld Devices,” ACM Multimedia '03 (Systems Track) (ACM  SIGMM -03), Berkeley, CA, 02-08 November 2003.

 
C111 M. Mamidipaka, K. Khouri, N. D. Dutt, and M. Abadir," IDAP: A Tool for High Level Power Estimation of Custom Array Structures," Proc. of Int'l Conference on Computer Aided Design (ICCAD), San Jose, CA November 2003.

 
C112 S. Gupta, M. Luthra, N.D. Dutt, R.K. Gupta, A. Nicolau, “Hardware and Interface Synthesis of FPGA Blocks using Parallelizing Code Transformations International Conference on Parallel and Distributed Computing and Systems, November 2003. (Invited Talk)

 
C113 M. Buss, T. Givargis and N.D. Dutt, “Exploring Efficient Operating Points for Voltage Scaled Embedded Processor Cores,” Proceedings of the 24th IEEE International Real-Time Systems Symposium (RTSS 2003), December 3-5, 2003, Cancun, Mexico.

 
C114 P. Mishra, A. Kejariwal, and N.D. Dutt, Synthesis-driven Exploration of Pipelined Embedded Processors, Proceedings of the 2004 International Conference on VLSI Design, Mumbai, India, January 5-9, 2004.

 
C115 A. Shrivastava and  N.D. Dutt, “Energy Efficient Code Generation Exploiting  Reduced Bit-width Instruction Set Architectures,” Proceedings of ASPDAC-2004, January 2004.

 
C116 S. Gupta, N.D. Dutt,  R. Gupta and A. Nicolau, “Loop Shifting and Compaction for the High-Level Synthesis of Designs with Complex Control Flow,” Proceedings of the 2004 Conference on Design, Automation and Test in Europe (DATE 2004), February 2004.

 
C117 P. Mishra and N.D. Dutt, “Graph-Based Functional Test Program Generation for Pipelined Processors,” Proceedings of the 2004 Conference on Design, Automation and Test in Europe (DATE 2004), February 2004.   

 
C118 I. Issenin, E. Brockmeyer, M. Miranda and N.D. Dutt, “Data Reuse Analysis Techniques for Software-Controlled Memory Hierarchies,” Proceedings of the 2004 Conference on Design, Automation and Test in Europe (DATE 2004), February 2004.

 
C119 A. Gordon-Ross, F. Vahid and N.D. Dutt, “Automatic Tuning of Two-Level Caches to Embedded Applications” Proceedings of the 2004 Conference on Design, Automation and Test in Europe (DATE 2004), February 2004.   

 
C120 N. Bansal, S. Gupta,  N.D. Dutt, R. Gupta and A. Nicolau, “Towards Network Topology Exploraiton of Mesh-Based Coarse-Grained Reconfigurable Architectures,” Proceedings of the 2004 Conference on Design, Automation and Test in Europe (DATE 2004), February 2004.

 
C121 H. van Antwerpen, N.D. Dutt, R. Gupta, S. Mohapatra, C. Pereira, N. Venkatasubramanian, and R. von Vignau, “Energy-Aware System Design for Wireless Multimedia,” Proceedings of the 2004 Conference on Design, Automation and Test in Europe (DATE 2004), February 2004.

 
C122 S. Banerjee and N.D. Dutt, “FIFO Power Optimization for On-Chip Networks,” Proceedings of the International Great Lakes VLSI Conference (GLVLSI-2004), Boston, April 2004.

 
C123 S. Pasricha, N.D. Dutt, and M. Ben-Romdhane, “Extending the Transaction Level Modeling Approach for Fast Communication Architecture Exploration,” Proceedings of the Design Automation Conference 2004 (DAC 2004),  San Diego, CA, June 2004.

 
C124 P. Biswas, L. Pozzi, K. Atasu, V. Choudhary, P. Ienne, and N.D. Dutt, “Introduction of Local Memory Elements in Instruction Set Extensions,” Proceedings of the Design Automation Conference 2004 (DAC 2004),  San Diego, CA, June 2004.

 
C125 A. Kejariwal, S. Gupta,  N.D. Dutt, R. Gupta and A. Nicolau, “Proxy-based Partitioning of Watermarking Algorithms for Reducing Energy Consumption in Mobile Devices,” Proceedings of the Design Automation Conference 2004 (DAC 2004),  San Diego, CA, June 2004.

 
C126 N. Bansal, S. Gupta, N.D. Dutt, R. Gupta and A. Nicolau, “Interconnect-Aware Mapping of Applications to Coarse-Grained Reconfigurable Architectures,” Proceedings of the 2004 Conference on Field Programmable Logic (FPL 2004), August 2004.

 
C127 N. Dutt and P. Mishra, “Functional Validation of Processors,” Proceedings of the 2004 EuroMicro Digital System Design Conference (DSD 2004), August 2004.
(Invited Keynote Paper)

 
C128 S. Pasricha, N. Dutt, M. Ben-Romdhane, “Fast Exploration of Bus-based On-chip Communication Architectures”, Proceedings of the International Symposium on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2004), Sep 8-10 2004.

 
C129 M. Mamidipaka, K. Khouri, N. Dutt, and M. Abadir, “Analytical Models for Leakage Power Estimation of Memory Array Structures,” Proceedings of the International Symposium on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2004), Sep 8-10 2004.

 
C130 S. Banerjee and N. Dutt, “Efficient search space exploration for HW-SW Partitioning,” Proceedings of the International Symposium on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2004), Sep 8-10 2004.

 
C131 A. Shrivastava, E. Earlie, N. Dutt, A. Nicolau, “Operation Tables for Scheduling in the presence of  Incomplete Bypassing,” Proceedings of the International Symposium on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2004), Sep 8-10 2004.

 
C132 P. Mishra, N. Dutt, and Y. Kashai, “Functional Verification of Pipelined Processors:  A Case Study,”  Proceedings of the 5th IEEE International Workshop on Microprocessor Testing and Verification (MTV-2004), Austin, TX, Sep. 9-10 2004.

 
C133 J. Seo and  N.D. Dutt, “A Generalized Technique for Energy-efficient Operating Voltage Set-up in Dynamic Voltage Scaled Processors,” Proceedings of ASPDAC-2005, January 2005.

 
C134 S. Pasricha, N.D. Dutt, and M. Ben-Romdhane “Automated Throughput-Driven Synthesis of Bus-Based Communication Architectures,” Proceedings of ASPDAC-2005, January 2005.

 
C135 A. Shrivastava, E. Earlie, N. Dutt, A. Nicolau, "PBExplore: A Framework for Compiler-in-the-Loop Exploration of Partial Bypassing in Embedded Processors" Proceedings of the 2005 Conference on Design, Automation and Test in Europe (DATE 2005), March 2005

 
C136 Partha Biswas, Sudarshan Banerjee, Nikil Dutt, Laura Pozzi, and Paolo Ienne, "ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement", Proceedings of the 2005 Conference on Design, Automation and Test in Europe (DATE 2005), March 2005

 
C137 P. Mishra and N.D. Dutt, "Functional Coverage Driven Test Generation for Validation of Pipelined Processors", Proceedings of the 2005 Conference on Design, Automation and Test in Europe (DATE 2005), March 2005

 
C138 I. Issenin and N.D. Dutt, "FORAY-GEN: Automatic Generation of Affine Functions for Memory Optimizations", Proceedings of the 2005 Conference on Design, Automation and Test in Europe (DATE 2005), March 2005

 
C139 M. Reshadi and N.D. Dutt, "Generic Pipelined Processor Modeling and High Performance Cycle-Accurate Simulator Generation", Proceedings of the 2005 Conference on Design, Automation and Test in Europe (DATE 2005), March 2005

 
C140 S. Mohapatra, R. Cornea, H. Oh, K. Lee, M. Kim, N. Dutt, R.Gupta, A. Nicolau, S. Shukla, N.Venkatasubramanian, "A Cross-Layer Approach for Power-Performance Optimization in Distributed Mobile Systems", Proceedings of the 19th IEEE/ACM International Parallel and Distributed Processing Symposium (IPDPS 2005), April 2005

 
C141 A. Gordon-Ross, F. Vahid and N.D. Dutt, "A First Look at the Interplay of Code Reordering and Configurable Caches", Proceedings of the IEEE/ACM 2005 Great Lakes Symposium on VLSI (GLSVLSI 2005), April 2005

 
C142 M. Kim, H. Oh, N. Dutt, A. Nicolau, N.Venkatasubramanian, "Probability-based Power Aware Error Resilient Coding", Proceedings of the First International Workshop on Services and Infrastructures for the Ubiquitous and Mobile Internet (SIUMI¹05), June 2005

 
C143 S. Pasricha, N.D. Dutt, E. Bozorgzadeh, and M. Ben-Romdhane, "Floorplan-aware Automated Synthesis of Bus-based Communication Architectures", Proceedings of the Design Automation Conference 2005 (DAC 2005), Anaheim, CA, June 2005. (BEST PAPER AWARD NOMINATION)

 
C144 S. Banerjee, E. Bozorgzadeh, and N.D. Dutt, "Physically-aware HW-SW Partitioning for Reconfigurable Architectures with Partial Dynamic Reconfiguration", Proceedings of the Design Automation Conference 2005 (DAC 2005), Anaheim, CA, June 2005

 
C145 K. Lee, N. Dutt, and N.Venkatasubramanian, "An Experimental Study on Energy Consumption of Video Encryption for Mobile Handheld Devices" IEEE International Conference on Multimedia & Expo (ICME 2005), Amsterdam, The Netherlands, July 2005

 
C146 S. Pasricha, N.D. Dutt and M. Ben-Romdhane, "Using TLM for Exploring Bus-based SoC Communication Architectures", Proceedings of IEEE 16th International Conference on Application-specific Systems, Architectures and Processors (ASAP-2005), Greece, July 2005

 
C147 A. Gordon-Ross, F. Vahid and N.D. Dutt, "Fast Configurable-Cache Tuning with a Unified Second-Level Cache", Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED-2005), San Diego, CA, August 2005

 
C148 A. Shrivastava, E. Earlie, N. Dutt, A. Nicolau, "Aggregating Processor Free Time for Energy Reduction", Proceedings of the International Symposium on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2005), September 2005

 
C149 H. Oh, S. Ha and N. Dutt, "Shift Buffering Technique for Automatic Code Synthesis from Synchronous Dataflow Graphs", Proceedings of the International Symposium on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2005), September 2005

 
C150 A. Kejariwal, S. Gupta, A. Nicolau, N. Dutt, and R. Gupta, "Energy Analysis of Multimedia Watermarking on Mobile Handheld Devices", Proceedings of the IEEE 2005 3rd Workshop on Embedded Systems for Real Time Multimedia (ESTIMEDIA 2005), New York, September 2005

 
C151 A. Shrivastava, I. Issenin and N.D. Dutt, "Compilation Techniques for Energy Reduction In Horizontally Partitioned Cache Architectures", Proc. Of the 2005 International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES-2005), San Francisco, CA, September 2005

 
C152 H. Oh, N. Dutt and S. Ha, "Single Appearance Schedule with Dynamic Loop Count for Minimum Data Buffer from Synchronous Dataflow Graphs", Proc. Of the 2005 International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES-2005), San Francisco, CA, September 2005

 

Workshops

W1 N.D. Dutt, “A Language for Designer Controlled Behavioral Synthesis,” 1989 ACM/IEEE Physical Design Workshop, Long Beach, CA, May 2, 1989 (Invitation-only workshop).

 
W2 N.D. Dutt, “Annotated Textual State Tables: An Intermediate Representation for Synthesis,” IEEE Design Automation Workshop, Scottsdale, AZ, Jan 22, 1990 (Invitation-only workshop).

 
W3 N.D. Dutt and J.R. Kipps, “Bridging High Level Synthesis to RTL Technology Libraries,” ACM/IEEE Fifth International Workshop on High Level Synthesis, Buehlerhoehe, Germany, March 1991 (Refereed by Program Committee).

 
W4 P.K. Jha and N.D. Dutt, “Rapid Estimation for Parameterized Components in High-Level Synthesis,” ACM/IEEE Sixth International Workshop on High Level Synthesis, Dana Point, CA, November 1992 (Refereed by Program Committee).

 
W5 P.K. Jha and N.D. Dutt, “Generic Component Sets and Rapid Technology Projection for High-Level Design Applications,” The 4th ACM/IEEE Physical Design Workshop, Lake Arrowhead, CA, April 1993 (Refereed by Program Committee).

 
W6 C. Ramachandran, P.K. Jha, F. Kurdahi and N.D. Dutt, “The Effects of Variations in Component Styles and Shapes on Functional Synthesis,” Proceedings of The International IFIP Workshop on Logic and Architecture Synthesis, Grenoble, France, December 1993. (Refereed by Program Committee)

 
W7 N.D. Dutt, “High-Level Synthesis for Real Architectures -- An Academic HLS View,” 1994 IEEE Winter VLSI Workshop, La Jolla, CA, April 1994  (Invited talk).

 
W8 S. Novack, A. Nicolau and N.D. Dutt, “A Unified Code Generation Approach Using Mutation Scheduling,” First Workshop on Code Generation for Embedded Processors, Schloss Dagstuhl, Germany, August 1994 (Invited talk and paper).

 
W9 D. Kolson, A. Nicolau and N.D. Dutt, “Register Allocation for Embedded Processors with Non-Uniform Register Files,” Second Workshop on Code Generation for Embedded Processors, Belgium, March 1996 (Invited talk).

 
W10 N.D. Dutt, “Software Synthesis for Embedded Systems: What’s new?,” 1996 Dagstuhl workshop on Design Automation for Embedded Systems, Schloss Dagstuhl, Germany, April 1996. (Invited talk)

 
W11 N.D. Dutt, Position Statement at the National Science Foundation Workshop on Future Research Directions in CAD for Electronic Systems: “Putting the `D’ Back in CAD,” Seattle, WA, May 13-14, 1996.

 
W12 A. Halambi, A. Nicolau and N.D. Dutt, “Retaining Semantic Information for Improved Code Generation,” Third Workshop on Code Generation for Embedded Processors, Haus Bommerholz, Witten, Germany, March 1998 (Invited talk).

 
W13 P. Grün, A. Nicolau & N.D. Dutt, "Automatic Generation of a Software Toolkit from EXPRESSION," Fourth Workshop on Software and Compilers for Embedded Systems, St. Goar, Germany, August 1999.  (Invited talk).

 
W14 A. Halambi, N.D. Dutt and A. Nicolau, "Customizing Software Toolkits for Embedded System-On-Chip," International IFIP Workshop on Distributed and Parallel Embedded Systems(DIPES2000), Paderborn University, Germany, October 2000. (Refereed by Program Committee)

 
W15 P. Grun, N.D. Dutt and A. Nicolau, "Aggressive Memory-Aware Compilation," The 2nd Workshop on Intelligent Memory Systems, In conjunction with ASPLOS-IX, Boston Massachusetts, November 12, 2000 (Reviewed by Program Committee)

 
W16 A. Halambi, A. Shrivastava, N.D. Dutt and A. Nicolau, "A Customizable Compiler Framework for Embedded Systems," Fifth Workshop on Software and Compilers for Embedded Systems (SCOPES 2001), St. Goar, Germany, March 2001 (Reviewed by Program Committee).

 
W17 P. Mishra, F. Rousseau, N.D. Dutt and A. Nicolau, “Architecture Description Language Driven Design Space Exploration in the Presence of Coprocessors,” Proceedings of the 10th  (SASIMI 2001), October 2001. (Refereed by Program Committee)

 
W18 P. Mishra, N. Krishnamurthy, N. Dutt and M. Abadir, “A Property Checking Approach to Microprocessor Verification using Symbolic Simulation,” Microprocessor Test and Verification (MTV), Austin, Texas, June 2002. (Refereed by Program Committee)

 
W19 R.  Cornea, S. Mohapatra, N.D. Dutt, R.K. Gupta, I. Kreuger, A. Nicolau, D. Schmidt, S.K. Shukla, and N. Venkatasubramanian, “A Model-Based Approach to System Specification for Distributed Real-time and Embedded Systems,” 9th IEEE Real-time/Embedded Technology and Applications Symposium Workshop on Model-Driven Embedded Systems, (RTAS 2003), Washington, D.C., May 2003.(Refereed by Program Committee)

 
W20 S. Mohapatra, R. Cornea,  N.D. Dutt, A. Nicolau, and N. Venkatasubramanian, “Power-Aware Multimedia Streaming in Heterogenous Multi-User Environments,” IFIP/IEEE International Workshop on   Concurrent Information Processing and Computing (CIPC 2003)  Sinaia, Romania, July 2003. (Refereed by Program Committee)

 
W21 R. Cornea, N.D. Dutt, R. Gupta, S. Mohapatra, A. Nicolau, C. Pereira, S. Shukla and N. Venkatasubramanian, “ServiceFORGE: A Software Architecture for Power and Quality Aware Services,” International Workshop on Service-Based Software Engineering (co-located with Formal Methods in Europe – FME), Pisa, Italy, September 2003. (Refereed by Program Committee)

 
W22 S. Pasricha, S. Mohapatra, M. Luthra, N.D. Dutt and N. Venkatasubramanian, “Reducing Backlight Power Consumption for Streaming Video Applications on Mobile Handheld Devices,” First Workshop on Embedded Systems for Real-Time Multimedia, Newport Beach, CA, October 3-4 2003. (Refereed by Program Committee)

 
W23 H. Tomiyama, H. Takada and  N.D. Dutt, “Data Organization Exploration for Low Energy Address Buses,” First Workshop on Embedded Systems for Real-Time Multimedia, Newport Beach, CA, October 3-4 2003. (Refereed by Program Committee)

 
W24 N. Bansal, S. Gupta, N.D. Dutt and A. Nicolau, “Analysis of  Coarse-Grain Reconfigurable Architectures with Different Processing Element Configurations,” Second Workshop on Application-Specific Processors (WASP’03), San Diego, CA, Dec. 2003. (Refereed by Program Committee)

 
W25 R. Cornea,  S. Mohapatra, N.D. Dutt, A. Nicolau, and N. Venkatasubramanian, “Managing Cross-Layer Constraints for Interactive Mobile Multimedia,” Workshop on   Constraint-aware Embedded Software,  Cancun, December 2003. (Refereed by Program Committee)

 
W26 P. Biswas, S. Banerjee, N. Dutt, L. Pozzi,  and P. Ienne,  “Fast Automated Generation of High-Quality Instruction Set Extensions for Processor Customization,” Third Workshop on Application-Specific Processors (WASP’04), Stockholm, Sweden, September 2004. (Refereed by Program Committee)

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