Graduate Research Assistant
Department of Computer Science
University of California, Irvine
Phone: +1(949)232-7349
aseemg@uci.edu

Research Summary

A high power dissipation of embedded systems no longer affects just the battery life of the system. High power densities manifest as high operating temperatures, which threaten the operability and reliability of chips. My research focusses on temperature aware design of Systems-on-Chips (SoCs) for reduced leakage power and enhanced system reliability during different stages of design flow.

At the system level, we have done research on:
  • Temperature and floorplan aware leakage estimation
  • Floorplanning for reducing leakage power
  • Floorplanning for enhanced SRAM reliability
  • Communication architecture (bus) based thermal management

  • At the microarchitectural level, we have done research on:
  • Power, performance, and thermal profiling of SMT processors
  • Thermal management of SMT processors
  • Reducing register file's peak temperature by regionalizing and access pattern redistribution
  • Leakage and temperature control of SRAM peripheral circuits
  • Thermal aware SRAM-design with power & reliability constraints

  • At the physical level, we have done research on:
  • Effect of temperature on SRAM reliability under the presence of process variations
  • Thermal aware global routing for enhanced reliability
  • Thermal aware cell Vt optimization
  • Thermal aware interconnect design
  • Thermal aware Design Rule Checking (DRC) to improve DFM (Design for Manufacturability)

  • Please visit the publications page for a list of papers.