CS 154 Lab

TA: Shreya Chippagiri (schippag@uci.edu) 

 Office hour:  Tu @ 11am  in 424F, ICS1 building



  Lab1 Hours:

Fri at 12

  Lab2 Hour:

Fri at 1pm

For announcements, please check the class website and the EEE message board.  Post your questions to the message board.


Here is a memory module with test program for lab 6. To use it, replace your mem.vhd with this mem file. You also need to change RAM_ADDR in Global_dcls.vhd from range 0 to 31 to range 0 to 63 because the memory is bigger now. After running the simulation for about 240000ns, your memory content from address 31 to 63 should look like this.


Lab Schedule


Specification Deadline

Program Deadline


Lab 0: an example




Lab 1: Combinational Design

April 7 at 11:45pm

April 11 at 11:45pm


Lab 2: Sequential Circuit

April 14 at 11:45pm

April 19 at 11:45pm


Lab 3: Register File

April 21 at 11:45pm

April 29 at 11:45pm


Lab 4: ALU and Basic Datapath

April 25 at 11:45pm

May 2 at 11:45pm


Lab 5: Complete Datapath

May 9 at 11:45pm

May 15 at 11:45pm


Lab 6: Complete MIPS Processor

May 23 at 11:45pm

June 5 at 11:45am


Lab 7: Synthesis







For each lab assignment, you are required to submit your work in THREE steps.

1.     submit the specification ("paper design") to EEE. This may be a truth table, FSM diagram, schematics, etc., as necessary to specify each lab assignment. You can turn in scanned image of your paper, or electronic documents (excel spreadsheets, Visio diagrams, etc).


2.     submit the vhdl files, both the design and the test bench, to EEE (zipped into a single file).

3.     demo to the TA what you have submitted (there will be demo sign up sheets). Demo must be done within one week after project deadline.



Submission format for EEE:

_       name a file with your student id

_       when submitting multiple files create a single zip file first.

_       Upload your (zip) file into your EEE lab folder.


Make sure to submit all required files - otherwise we will not be able to grade your assignment



Your final grade for the course CS 154 will depend on class participation (attendance of class and lab) and lab assignment grades. A lab will have a score of  100pts. Each lab will have a different weight in the final grade computation based on its complexity.


Lab scoring

_       Specification 20%

o   Clearly specify your design, you may use truth table, logic function, and/or block diagrams in your specification.


_       VHDL design - 40%

o   Make sure what you submit is the final working code.  With comments!

_       Test bench - 20%
Make sure to have enough test cases to cover different situations.

_       Comments - 5%

_       Demo        - 15%

The demo is required. You will lose 50% of your total lab score if you don't demo your work.


Late Submission

The later labs depend on earlier ones, so the deadlines of each lab will be strictly enforced. If you are not able to finish a lab, submit the latest version you have BEFORE the deadline, and you will be given partial credit.


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