International Workshop on Innovative Architecture for Future
Generation High-Performance Processors and Systems

Date: January 27-29, 2003
Place: Kauai, Hawaii
Location: Sheraton Hotel

Sponsored by the Center for Embedded Computer Systems, UC Irvine

Program Committee

Prof. Hideo Amano, Keio U
Prof. Makoto Amamiya, Kyushu U
Prof. Kei Hiraki, Tokyo U
Dr. Bill Gropp, Argonne
Prof. Peter Kogge, Notre Dame
Prof. Alex Orailoglu, UCSD
Prof. Constantine Polychronpoulos, CSRD/UofI
Prof. Hiroshi Nakashimar, Toyohashi Inst.
Prof. Hironori Kasahara, Waseda
Prof. Shuichi Sakai, Tokyo U
Prof. Kyle Gallivan, Florida State
Prof. Mateo Valero, UPC Spain
Prof. Alex Veidenbaum, UC Irvine
Prof. Takanobu Baba, Utsunomiya U
Prof. K. Joe, Nara Women's Univ., Japan
Prof. Hironori Nakajo, TUAT

Local Arrangements Chair: Prof. Nakajo
Finance Chairs: Profs. Nicolau and Joe
Publication Chair: Prof. Veidenbaum

Workshop description
Submission
Participants
Local Arrangements
Preliminary Program

IWIA Steering Committee


Description

This invited workshop aims to bring together researchers and designers from academia and industry to discuss directions in the development of high-performance, parallel, distributed, and multimedia processors and systems. The workshop invitees are computer architects and compiler, operating system, and application experts. The main goal of the workshop is to discuss future trends in the development of architecture and software systems and to explore the assumptions made by the architects about software systems and by software writers about architecture. The increased complexity in each of these areas calls for increased interaction with researchers from all of the other disciplines to accurately assess the potential directions and future trends in architecture and systems.

The main themes of the workshop are software- and technology-driven and constrained new architectures, compiler/architecture interaction and co-design, and application requirements and characteristics. Both numerical and non-numerical applications, such as database, data mining, Web- and Java-based, and (high-performance) embedded applications, are of interest. In all cases a longer-term view and assessment of the future is of most interest.

This year's special focus is embedded processors and systems. Today's embedded processors and systems are no longer based on just 4- and 8-bit micro-controllers. At the high end they include 64-bit, 1GHz processors like SiByte1250 and many different 32-bit processors optimized for particular domain and designed to consume very little power. There are also parallel embedded systems, from sensor arrays to networks of routers. In addition, many of the embedded processors are truly systems on a chip (SOC), containing a variety of I/O interfaces and controllers. Again SiByte1250 and StrongArm/Xscale family are excellent examples of high levels of integration.

Optimization and customization of such systems is the topic of this year's workshop. As usual, memory hierarchy is one of the major sources of both performance and power problems in embedded systems. In particular, architectural innovation and compiler support for embedded processors and systems are major challenges. Workshop topics of interest include but are not limited to:

Additional workshop areas of interest include the perennial favorites below, but preference will be given to submissions on the above-mentioned topics.

The workshop will consist of sessions combining individual presentations with discussion. Presentations will be limited to ~20 min to provide sufficient time for discussion. An ideal presentation will concentrate on trends and future directions in addition to recently obtained results. Speculation is encouraged.

Workshop participation is capped at 25 invitees.

Submission and Publication

The invitees wishing to make a presentation should submit an extended abstract, up to 3 pages, by 1/6/03. Submissions should be electronic in postscript or pdf format. The abstracts will be reviewed and printed in the on-site proceedigns.

The final proceedings consisting of full papers will be published by IEEE Computer Society Press after the meeting. The papers will undergo an additional review process and be selected for publication in the post-proceedings. Papers will be due by ~April 1st 2003.
The following set of LaTex macros should be used in preparing the final paper. Additional publication instructions will be made available at a later date.

Participants

USA

To be announced

To be announced