International Workshop on Innovative Architecture for Future
Generation High-Performance Processors and Systems

Date: Nov. 1-3, 1999
Place: Maui, Hawaii
Location: Maui High Performance Computing Center

Program Committee

Dr. Utpal Banerjee, Intel
Prof. Andrew Chien, UC San Diego
Prof. Kyle Gallivan, Florida State .
Prof. Dennis Gannon, Indiana .
Prof. William Gropp, Argonne
Dr. Robert Lucas, NERSK
Prof. Brian Smith, UNM/MHPCC
Prof. Guri Sohi, Wisconsin
Prof. Alex Veidenbaum, UC Irvine
Prof. Makoto Amamiya, Kyushu U.
Prof. Hiroshi Nakashima, Toyohashi U. of Tech.
Prof. Hironori Kasahara, Waseda U.
Prof. Hiroshi Nakamura, U. of Tokyo
Prof. K. Joe, Nara Women's Univ.

Local Arrangements Chair: Prof. H. Nakajo, Tokyo U. of Agriculture and Technology

Workshop description
Submission
Participants
Local Arrangements
Preliminary Program




Description

This invited workshop aims to bring together researchers and designers from academia and industry to discuss directions in the development of high-performance, parallel, distributed, and multimedia processors and systems. The workshop invitees are computer architects and compiler, operating system, and application experts. The main goal of the workshop is to discuss future trends in the development of architecture and software systems and to explore the assumptions made by the architects about software systems and by software writers about architecture. The increased complexity in each of these areas calls for increased interaction with researchers from all of the other disciplines to accurately assess the potential directions and future trends in architecture and systems.

The main themes of the workshop are application requirements and characteristics, compiler/architecture interaction and codesign, and software- and technology-driven and constrained new architectures. Numerical and non-numerical applications, in particular database, data mining, Web- and Java-based applications, are of interest. In all cases a longer-term view and assessment of the future is of most interest.

This year we will concentrate on computation and memory intensive applications, i.e. applications requiring more CPU power, more memory bandwidth and lower memory latency than present or projected systems can provide. Workshop topics of interest will deal with this type of applications and include but are not limited to:

Additional workshop areas of interest include the perennial favorites below, but preference will be given to submissions on the above-mentioned topics.

The workshop will consist of sessions combining individual presentations with discussion. Presentations will be limited to 15 min to provide sufficient time for discussion. An ideal presentation will concentrate on trends and future directions rather than recently obtained results. Speculation is encouraged.

Workshop participation is capped at 50 invitees.
RSVP by Sept.30th, 1999 if you plan to attend.

Submission and Publication

An extended abstract, up to 3 pages, should be submitted by 10/10/99. Submissions should electronic and in postscript or pdf format. Papers will be refereed on the basis of the extended abstract and accepted for either regular or short presentation. Authors will be notified about paper acceptance by Oct. 21, 1999.

Full papers will be published by IEEE Computer Society Press after the meeting. The full papers will undergo an additional review process. The following set of LaTex macros should be used in preparing the paper. Additional publication instructions will be made available at a later date.

Participants


USA

To be announced
To be announced