AMRM: Project Technical Approach
Outline
Technology Evolution
Consider Interconnect
Rethinking Circuits When Interconnect Dominates
Implications: Circuit Blocks
Implications: Architectures
Opportunity: Application-Adaptive Architectures
Architectural Adaptation
Adaptation Challenges
Why Cache Memory?
4-year technological scaling
PPT Slide
Impact of Memory Stalls
Opportunities for Adaptivity in Caches
Opportunities - Cont’d
Applying Adaptivity
Where to Implement Adaptivity?
Where to Implement?- Cont’d
Where to Implement - Cont’d
Current Investigation
Mechanisms Used (L1 to L2)
Mechanisms Used - Cont’d
Configurations
Observed Behavior
Possible Adaptive Mechanisms
Adaptive Hardware - Cont’d
Adaptivity via compiler
Further opportunities to adapt
The AMRM Project = Compiler, Architecture and VLSI Research for AA Architectures
Summary
Appendix: Assists Being Explored
Victim Caching
Victim Cache
Stream Buffer
Stream Cache
Stride Prefetch
Miss Stride Buffer
Advantage over Victim Cache
Architecture Implementation
Prefetch Scheduler
Pointer Stream Buffer
Appendix: Prefetching Adaptation Results
Prefetching for Latency & BW Management
Adaptation for Latency Tolerance
Prefetching Experiments
Adaptation for Bandwidth Reduction
Simulation Results: Latency
Simulation Results: Bandwidth
Email: rgupta@ics.uci.edu
Home Page: http://www.ics.uci.edu/~rgupta