Retargetable Pipeline Hazard Detection for Partially Bypassed Processors

Aviral Shrivastava , Nikil Dutt , Alex Nicolau , and Eugene Earlie,

IEEE TVLSI: IEEE Transactions on Very Large Scale Integrated circuits

Abstract: Register bypassing is a widely used feature in modern processors to eliminate certain data hazards. Although complete bypassing is ideal for performance, it has significant impact on the cycle time, area, and power consumption of the processor. Owing to the strict design constraints on the performance, cost and the power consumption of embedded processor systems, architects seek a compromise between the design parameters by implementing partial bypassing in processors. However, partial bypassing in processors presents challenges for compilation. Traditional data hazard detection and/or avoidance techniques used in retargetable compilers that assume a constant value of operation latency, break down in the presence of partial bypassing. In this article, we present the concept of Operation Tables that can be used to accurately detect data hazards, even in the presence of incomplete bypassing. Operation Tables integrate the detection of all kinds of pipeline hazards in a unified framework, and can therefore be easily deployed in a compiler to generate better schedules. Our experimental results on the popular Intel XScale embedded processor running embedded applications from the MiBench suite, demonstrate that accurate pipeline hazard detection by Operation Tables can result in up to 20% performance improvement over the best performing GCC generated code. Finally we demonstrate the usefulness of Operation Tables over various bypass configurations of the Intel XScale.