An Efficient Compiler Technique for Code Size Reduction using Reduced Bit-width ISAs

Ashok Halambi , Aviral Shrivastava , Partha Biswas , Nikil Dutt , and Alex Nicolau

DATE 2002: Proceedings of the International Conference on Design Automation and Test in Europe

Abstract: For many embedded applications, program code size is a critical design factor. One promising approach for reducing code size is to employ a "dual instruction set", where processor architectures support a normal (usually 32 bit) Instruction Set, and a narrow, space efficient (usually 16 bit) Instruction Set with a limited set of opcodes and access to a limited set of registers. This feature, however, requires compilers that can reduce code size by compiling for both Instruction Sets. Existing compiler techniques operate at the function-level granularity and are unable to make the trade-off between increased register pressure (resulting in more spills) and decreased code size. We present a profitability based compiler heuristic that operates at the instruction-level granularity and is able to effectively take advantage of both Instruction Sets. We also demonstrate improved code size reduction for the MIPS 32/16 bit ISA, using our technique. Our approach more than doubles the code size reduction achieved by existing compilers.