SUDARSHAN BANERJEE

Interests:                  HW-SW (hardware-software), FPGAs, Partitioning/Scheduling
Contact e-mail:        b a n e r j ee@ics.uci.edu

Status (03/2007):     Completed Ph.D. requirements                             

Some work in the not-very-distant past .... [List of publications]

S Banerjee, E Bozorgzadeh, J Noguera, N Dutt, "Selective Bandwidth and Resource Management in Scheduling for Dynamically Reconfigurable Architectures", DAC, San Diego (California), June 2007, pp 771-776

M Kim, S Banerjee, N Dutt, N Venkatasubramaniam, "Design Space Exploration of Realtime Multimedia MPSoCs with Heterogeneous  Scheduling Policies", ACM/IEEE CODES+ISSS, Seoul, Oct 2006, pp 16-21

S Banerjee, E Bozorgzadeh, N Dutt, "PARLGRAN: Parallelism granularity selection for scheduling task chains on dynamically reconfigurable architectures", ASP-DAC, Yokohama (Japan), Jan 2006, pp 491-496

S Banerjee, E Bozorgzadeh, N Dutt, "Physically-aware HW-SW Partitioning for reconfigurable architectures with partial dynamic reconfiguration", DAC, Anaheim (California), June 2005, pp 335-340

P Biswas, S Banerjee, N Dutt, L Pozzi, P Ienne, "ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement", DATE, Munich, Mar 2005, pp 1246-1251