Discussion Hour: |
TBD |
Lab1 Hour: |
Monday + Wednesday 4:30 - 5:50 pm @ ICS 183 |
Lab2 Hour: |
Tuesday + Thursday 5:00 - 5:50 pm @ ICS 189 |
Office Hour: |
Mon Tue Wed Thur 6:00-6:30 pm, in the lab |
For announcements, please read your UCI mail
Lab |
Specification Deadline |
Program Deadline |
Discussion |
Weight |
| Lab 0: an example | N/A | N/A | N/A | 0% |
| Lab 1: Combinational Design | 3pm, Apr 9 (Monday) | 11:45pm Apr 13 (Friday) | N/A | 5% |
| Lab 2: Sequential Design | 3pm, Apr 16 (Monday) | 11:45pm Apr 20 (Friday) | Slides | 5% |
| Lab 3: Register File | 3pm, Apr 23 (Monday) | 11:45pm, Apr 27 (Friday) | Slides | 15% |
| Lab 4: ALU & Data path | 3pm, Apr 30 (Monday) | 11:45pm, May 8 (Tuesday) | Slides | 15% |
| Lab 5: Complete Data path | 3pm, May 9 (Wednesday) | 11:45pm, May |
Slides | 20% |
| Lab 6: Complete MIPS Processor | 3pm, May 21 (Monday) | 11:45pm, June 1 (Friday) | FSM | 20% |
| Lab 7: Synthesis | N/A | 11:45pm, June 8(Friday) | N/A | 10% |
To start:
- Open ModelSim-Altera.
- Create a new project (File -> New -> Project) by
assigning project name and selecting location for the project.
- Add existing files lab1.vhd and lab1_tb.vhd to the project.
- Plug in your code in both the VHDL files.
- Change compilation order of the VHDL files if necessary by Compile
-> Compile Order (lab1.vhd should be compiled first followed by
lab1_tb.vhd).
- Compile the VHDL files by Compile -> Compile All.
- Set up simulation by Simulate -> Simulate...(here choose
work.lab1_tb as the entity to be simulated).
- Run simulation by Simulate -> Run -> Run-All. After
some time, stop execution by Simulate -> Break. If there is an
error, a message will be displayed.
Do not forget: the order of compilation is important!
Download ModelSim software, click here. If nothing happens after you run the installation file, try rebooting your computer. A tutorial for the software is also available on the same page.
Each group should only submit one copy of their work to EEE.
For each lab assignment, you are required to present your work
in THREE steps.
- submit the specification (paper design) to EEE. This may include
truth table, FSM diagram,
schematics, etc., which will be specified in each lab assignment. You
can turn in scanned image of your paper, or electronic documents (excel
spreadsheets, Visio diagrams, etc). Each group should only submit one
copy of the specification.
- submit the vhdl files, both the design and the test bench, to EEE.
Each group should only submit one copy of the design files.
- demo to the TA what you have submitted during lab/office hour. Demo
must be done within one week after project deadline.
For each submission on EEE:
- create a zip file and name it with your student id number
- put the required files into the zip file.
- upload your zip file into the folder.9
If I were submitting Lab 1, I would zip my .vhd files
(lab1.vhd and lab1_tb.vhd) and screen shot (wave.jpg) into 590*****.zip,
and upload it to the folder that belongs to Lab 1.
Make sure to submit all required files - otherwise we will not be able to grade your assignment
Your final grade for the course CS 154 will depend on class participation (attendance of class and lab) and lab assignment grades. Each lab, you will receive a score of 0-50 scale. Each lab will have a different weight in the final grade due to the difference in difficulty and complexity.
For each lab, the following aspects will be considered:
About demo
You will lose 50% of your grade if you don't demo your work. For example, if someone receives 90 points for lab1, but he did not demo his work, he will only get 45 points.About late work
Since we are going to do many projects, and the later ones depend on earlier ones, deadline of each project will be strictly enforced. If you are not able to finish a project, submit the latest version you have BEFORE the deadline, and you will be given partial credit.