4-bit Vote Tallying Circuit

Lab 1

The objective of this lab assignment is to get familiar with VHDL and to learn the use of ModelSim-Altera CAD tools.

Please read ALL instruction carefully. Only properly submitted assignments will be graded. Make sure to create a zip file, named by your student id, and submit your files in it.

Specification - Due Monday, 4/9/2012 at 3pm.

A vote tallying circuit counts the number of 1's in the input signal. The 4-bit tally circuit we are designing has 4 input bits: X0, X1, X2, X3.  Please specify the circuit with a truth table. You can name the output bits by Y0, Y1, ... Yn. Then produce a 'sum of products' expression for each output bit.

You should think about these questions when specifying the truth table:

1. Based on the number of bits in the input, how many rows should the truth table have?
2. When tallying 1's in the 4 bit input, what's the range of the result? (   )
   a) 1 to 4    b) 0 to 4    c) 0 to 3    d) 0 to 3
3. Based on your answer for question 2, how many bits is required to encode the result in binary?

Lab team sign up - Due Wednesday, 4/11 at 11:45pm.

Design - Due Friday, 4/13 at 11:45pm

Your task is to design a 4-bit tally circuit and a test bench to test the functionality of the module. The template VHDL files for the tally module (lab1.vhd) and the test bench (lab1_tb.vhd) have been provided to you. The interface (that is, ports) is already defined. You need complete the design in both files. Please do not make any changes to the interface.

The tally module (that is, the lab1 entity) has one 4-bit input and one 3-bit output. The interface (ports) is defined as below for the lab1 entity in lab1.vhd file. - Inputs x : in STD_LOGIC_VECTOR(3 downto 0) - Output y : out STD_LOGIC_VECTOR(2 downto 0)

The design of assignment 1 should be based on basic logic gates: OR, AND, and NOT. You are required to implement the tally module as a combinational circuit using concurrent signal assignments in VHDL.

Start by downloading lab1.zip and unpacking it.

Verification - Due Friday, 4/13 at 11:45pm

Inside the test bench, you should test your tallying module using various input combinations. At each specific interval of time (which can be in the order of some tens of nanoseconds for example), change the input, get the result from the tallying module and compare the product with the expected value to see if it is correct. In case the result does not match the expected value, the test bench should generate an error message. Use the ASSERT statement for reporting the error message. Note that the entity lab1_tb in the test bench does not have ports since there are no input and output signals to it.

1. A specification for your design, including the truth-table and the logic expressions.

2. Your VHDL design.
3. Your VHDL test-bench.
4. Screenshots of the waveforms for all in/out signals in the design.