The objective of this lab assignment is to design a sequential circuit. You will submit your specification and your VHDL code through EEE.
Please read ALL instructions carefully. Only properly submitted assignments will be graded. Each group should only submit one copy. Don't forget to mention your partner's name in the files.
Specification - Due Monday, 4/16/2012 at 3pm.
Your task is to design a 3-bit counter that counts by an increment of 5. A counter generates a series of numbers with each clock cycle. Regular 3 bit counters would increment the couter value by 1 every interval and the output would be 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 ... and continue to repeat. Our by-5 counter increments the counter value by 5 each time, and the output would be 0 5 2 7 4 1 6 3 0 5 ...The design should consist of 2 parts, a combinational circuit that "computes" the next value based on the current value, which we call it the "calculator"; and a sequential circuit that "remembers" the current value and "updates" to the next one with clock, which we call it the "register".
First, you should specify the calculator with a truth table, then write down the logical expression. Feel free to simplify the expression. Name the input signal C (as in current) and the output signal N (as in next). Draw a gate-level schematic for your optimized expression.
Second, you should show how to connect the register with the calculator, as well as reset and clock signals, in a block diagram. There are 4 ports to the register: reset, clock, input, and output. There are 2 ports to the calculator: current and next.
Design - Due Friday, 4/20/2012 at 11:45pm.
Download lab2.zip and unpack it.
The by-5 counter module (that is, the lab2 entity) has two 1-bit inputs (clk and reset_N) and one 3-bit output (count). The rising edge of the clock signal clk triggers the counter to the next value. The reset signal reset_N sets the output of the counter to 0 asynchronously, which means counter value chages to 0 immediatly when reset signal arrives, even without the clock trigger. Remember, reset_N is a low-active signal.
Your VHDL design should consist of a combinational logic section implemented via concurrent signal assignments (i.e. using logical gates such as AND, OR, NOT, etc.) and a register update process.The top level of your design should be called lab2 and needs to have the following ports (in the same order as given here, with the same names):
Inputs:
clk: std_logic
reset_N: std_logic
Outputs:
count:std_logic_vector (2 downto 0)
Name and order of the ports in your design is important. To receive full credit please follow the order and assign names as above.
Verification Due Friday, 4/20/2012 at 11:45pm.
Your test bench should generate a clock signal. The clock cycle time should be 10 ns.
First, verify the counting functionality by applying at least 10 clock signals to the counter. You should try to start couting from different values. Take 2 screen shots for 2 different inital values.
Second, verify the reset siganl can reset the counter to zero asynchronously. Also veryfy that the counter would start counting again after the reset signal is removed. The reset signal may not necessarily change at the same time as the clock. Take a screen shot of the waveform.
Please submit your design and verification by Friday, 4/20/2012 at 11:45pm.