Register File

Lab 3

The objective of this lab assignment is to design and implement a register file. 

The register file implements 32 registers, each of which is 32 bits wide. Register number 0 is a zero register; its content is always 0 and cannot be changed. Register 1 through 31 store any value assigned to them. Access to registers beyond 31 is not allowed.

We use data, address and control ports to interface with the register file. There should be 3 data ports: 2 for reading and 1 for writing. During each clock cycle, values from 2 registers can be read through the 2 read ports (d_out_1 and d_out_2) and 1 can be written through the write port (d_in). All 3 data ports are 32-bit wide.

Use address ports rd_addr_1, rd_addr_2 and wr_addr to supply addresses of registers that will be read from or written to. For example, if rd_addr_1 is set to 1 and rd_addr_2 is set to 3, then the value in register 1 and 3 can be read from data port d_out_1 and d_out_2 at the same time.

In addition to these ports, your register file needs to use a wr_en control signal to write the value on port d_in to a register addressed by wr_addr in the register file. The register file also needs a clock signal (port clk). Write operations are synchronized with this clock. 

You will need an array of vectors to implement the register file.

Specification - Due Monday, 4/23/2012 at 3pm.

Draw a block diagram of the register file as is described above. To make things easier, the register file has only 8 registers. You can represent the middle registers with ... and show only register 0, 1, 2 ... and 7

The register write_enable signal literally enables writing to the register. When each rising edge of the clock signal arrives, the register will only update its value if wr_en = 1. Otherwise, nothing will hapen.

Figure 1. 32 bit register with write-enable.

The MUX selectes one of the 8 inputs and sends it to the output, according to the 3-bit selection signal on the left.

Figure 2. Multiplexer with 8 32-bit inputs.

The 3-to-8 decoder, when enabled, "translates" the 3-bit input (for example, an address) into one of the 8 outputs (for example, to drive 8 enable siganls for 8 different devices).

Figure 3. 3-8 decoder. 

Pay attention to the wiring. Label the wires with proper signal names and mark the width.

Design - Due Friday, 4/28/2012 at 11:45pm.

The template VHDL files have been provided to you. The interface (that is, ports) is already defined. You need to add code for functionality in both files to make them work. Do not make any change to the interface.

Since we are using an array to implement the register file, the decoder and the mux component is implemented automatically by the array reference. The implementation should be very straight-forward. Please refer to Prof. Veidenbaum's slides (Slide #5 and #6 of Lecture 5). Our register file should be something like:
                                RegFile: array (0 to 31) of std_logic_vector(31 downto 0);
The declaration in the slides has many named subtypes and constants. Some of them are useful, and it will be a good idea to keep the declarations in a seperate package for future labs.

Index to array elements should be of type "INTEGER". To convert a signal of type STD_LOGIC_VECTOR to integer, you should use funciton "TO_INTEGER". It is declared in "IEEE.NUMERIC_STD" package. The argument of this function should be either STD_LOGIC_UNSIGNED or STD_LOGIC_SIGNED. So we woudl first cast our STD_LOGIC_VECTOR to STD_LOGIC_UNSIGNED, then pass it to TO_INTEGER. For example, to use wr_addr as array index, you should use: RegFile( TO_INTEGER( UNSIGNED(wr_addr) ) );

You should use a process to implement the writing operation. Think about which signals should be in the sensitivity list (wr_addr, wr_en, d_in, clk). Pay special attention to R0. When wr_addr = "00000", an update should not happen.

Verification - Due Friday, 4/28/2012 at 11:45pm.

In your test bench, you need to test your register file module for the following aspects:

Addressing: You must make sure that you are reading from / writing to the specific register you want. All addresses and data ports need to be tested. This has to be done first, because the following tests will test each register and to do that you must make sure you are able to access each register.
You should write unique values to different registers, and read from them and see if what you read is what you have written.

Content: You must make sure that each register holds what was actually written. No "stuck at" errors exist. Each bit in each register must be tested.
You should write "000...0" and "111...1" to each register and read from them and see if what you read is what you have written.

All input signals in test bench should be 1 clock long and go high a short time after a rising clock edge. Use assert instruction and expected values to detect errors.

1. A block diagram of the register file you designed that has 8 registers.

2. Your VHDL design.
3. Your VHDL test-bench.
4. screen shots of addressing and content tests.

Please submit your design and verification by Friday, 4/27/2012 at 11:45pm.