The objective of this lab assignment is to design and implement the ALU and design a basic data path consisting of a Register File and an ALU.
Please read ALL instructions carefully. Only properly submitted assignments will be graded. Make sure to create a zip file, named by your student id, and submit required files in it.
Your task is to make an Arithmetic Logic Unit(ALU) to execute a subset of MIPS ISA.
The instructions this ALU executes include:
| Name | ALU Control | Instruction Syntax | Description (in C code) |
| ADD | 000 | ADD rd, rs, rt | rd = rs + rt; |
| SUB | 001 | SUB rd, rs, rt | rd = rs - rt; |
| SLL | 010 | SLL rd, rs, C * | rd = rs << C; |
| SRL | 011 | SRL rd, rs, C * | rd = rs >> C; |
| AND | 100 | AND rd, rs, rt | rd = rs & rt; //bit-wise and |
| OR | 101 | OR rd, rs, rt | rd = rs | rt; //bit-wise or |
| XOR | 110 | XOR rd, rs, rt | rd = rs ^ rt; //bit-wise xor |
| NOR | 111 | NOR rd, rs, rt | rd = ~(rs | rt) |
To support the above instructions, we use data, control and status ports to interface with the ALU. You are required to use 3 data ports: 2 for input (A and B) 1 for output(C). All 3 data ports are 32 bits wide.
Use control ports func for operation selection. For example, if ALU Control is set to "000", then do addition.
In addition to these ports, your ALU needs to use a zero status signal to represent the situation when computation result is 0.
The basic data path contains the register file designed in lab 2 and the ALU. To coordinate the data communication, 3 more registers are added to the data path. Register A is between register file d_out_1 and ALU input A. Register B is between register file d_out_2 and ALU input B. Register ALUout is used to store the output of ALU. All these registers are synchronized with the global clock signal, so is the register file.
You are required to submit, in the specification, the following diagrams:
1.Block
diagram showing the internal logic of an 8-bit ALU. Show the details of
bit 0, 1, ... 6, 7 and use "..." to represent the ones in the middle.
You can use the following basic
components in your schematic: logic gates (AND, OR, XOR, NOT, NOR),
full adder, decoder and MUX. You need to come up with some logic to
implement both ADD and
SUB using the same full-adder (Hint: think about 2's compliment).
2. the block diagram of your data path. Name the signals properly.
Please pay attention to signal width. Don't forget to mark them!
Your task is to design the ALU module and assenble the datapath.
The template VHDL files for both module (ALU.vhd and datapath.vhd) and the testbench (ALU_tb.vhd and datapath_tb.vhd) have been provided to you. The interface (that is, ports) is already defined. You need to add code for functionality in both files to make them work. Do not make any change to the interface.
The first part of this lab is to design the ALU.
-You should put the entire ALU into a process.
-Use case statement to select different operations.
-You can use packages discussed in class.
The second part of this lab is to design the datapath.
-In your top level design, declare components for Register file and ALU and add the registers A,B,and ALUout.
- Click here for a reference datapath design.
In your ALU test bench, you need to test your ALU module for each operation with a few random inputs.
In your datapath test bench, you need to build a test case that writes some values in to the register file and executes some computation with the data in the register file. Pay attention to clocking.
-Specification by Monday, April 30 at 3pm.
-VHDL Design by Tuesday, May 8 at 11:45pm.