Please read ALL instructions carefully. Only properly submitted assignments will be graded. Make sure to create a zipfile, named by your student id, and submit required files in it.
In this lab you will complete the design of the data path by adding all the hardware necessary to support LD, ST, BNE, BEQ, and JMP instructions. The semantics and data path hardware needed for all of these are described in lecture notes, please consult those before proceeding. All of the instructions in the following table should to be implemented in this design.
Please turn in a block diagram of the data path.
Your task is to design the complete datapath and a testbench to test the functionality of the module.
This is a sample datapath design.
The template VHDL files for the module (lab5.vhd), global declaration package (Glob_dcls.vhd) and memory module (Mem.vhd) have been provided to you. The interface (that is, ports) is already defined. You need to add code for functionality in both files to make them work. Do not make any change to the interface.
Please see the updated glob_dcls.vhd here. Line 21 has been modified. The range should be "0 to 31" instead of "31 downto 0".
You need to test the following:
Generate the control signals in the right time in your testbench for each test case. As explained earlier, take clock period as 40 ns (which means, the time interval between two consecutive rising edges is 40 ns).
-Block diagram due Wednesday, May 9 at 3pm (EEE dropbox or in class).
-Make a zip file containing the ALL files (VHDL design and VHDL
test bench) of lab5 and submit it electronically via EEE. Due Tuesday,
May 15 Friday, May 18.
Both the implementation and test code will be graded. You will also be graded on coding style and code comments.