Datapath Synthesis and Gate-level simulation

Lab 7

Please read ALL instructions carefully. Only properly submitted assignments will be graded. Make sure to create a zip file, named by your student id, and submit required files in it.

Download this file to start. It contains 2 directores: "Syn" for synthesis and "Sim" for simulation.

Synthesis

In this lab, you will synthesis the whole datapath with QuartusII design tool. The goal of VHDL language is to describe hardware. What we've been doing until now are only inside the simulator. The synthesis process will transform what happens in the simulator into real hardware. It translates high-level VHDL code (if statements, case statements, etc...) into gate-level description that are specific for each device we want to program. Using such information, we will be able to simulate at gate level, with more realistic information (delays etc). We may also program an actual device.

First, create a new project in Quartus II. Please use the "new project wizard".

When you start the program, a window will pop out, click "Create a new project"
In the next screen, put in the project directory, project name, and top-level entity name. The top-level entity name should be "datapath" unless you change it.
In the next screen, add all the files. You can the "..." button besides the "File Name" box to browse. Use the "SYN" directory from the zip file.
In the next scree, selecte the device we want to target our design to. We will choose the family "Cyclone IV E" and select "Auto device selected by the Fitter". The design tool will find the device where our design can fit.
In the next scree, select the tool change like this:
click Finish and you are done.

Now we've have our project set up in Quartus II. Now edit your program. There are some changes we have to make to make our project synthesisable:

Memory model is changed. We added a clock signal to memory. Now memory operation is synchronized with the falling edge of the clock. (Why falling edge?)
We added an output port to the datapath to help debug. Because the synthesis tool will re-organize the design. The signals will disappear. In order to see what happens after synthesis, we have to specificly asign a signal to the port. This could shou contents in ALUOut, RegA, RegB ... depending on your needs when you debug.

After you are done editing, we can start the synthesis process by clicking this button: synthesis button

Simulation

The synthesis tool will generate a gate-level VHDL code as well as the delay information. We could simulate this gate-level VHDL code, with delay information, with our controller, in Modelsim.

First, create a new project with the files in the "Sim" derectory.

Second, add the DATAPATH.VHO file generated by the synthesis tool to the project. It should be located under "Syn\simulation\modelsim".

Next, start simulation. In the "Start Simulation" window, click the "SDF" tab, and add the delay information file. like this: (Remember to use INSTANCE names to correctly identify your datapath in the "Apply to Region" box.)

Add signals to the waveform and simulate.

Submission:

A synthesis report including:

Device Name
Total logic elements used
Total registers used
Total pins used
Total memory bits used
Maximum frequency.

Screen shots capturing Modelsim Simulation. Choose 3 instructions. Show the delays in signal change.

Make a zip file containing the above files and submit it electronically via EEE. Due Friday, Jun 8.