DUHDe 2017 — 4th Workshop on Design Automation for Understanding Hardware Designs

March 31, 2017 — Friday Workshop at DATE 2017, Lausanne, Switzerland

Scope and Target Audience

The design process is essentially a creative process which is reliant on the ability of designers to balance the interactions between a complex set of constraints to arrive at successful solutions. In order for designers to manage this task, they must collectively have a complete understanding of the behavior of the system, the mapping between behavior and structure, and the impact of each design feature on constraints such as power, performance, cost, and security. Design tasks require reasoning across multiple levels of abstraction in order to determine the impact of high-level design decisions, or to trace a design characteristic back to the feature which caused it. In a real design, cross-abstraction reasoning is difficult because the relationships between the different abstractions of a design are not captured. Designer time is expended discovering these cross-abstraction relationships in order to perform design, verification, and maintenance tasks. This workshop will present the state-of-the-art in Design Understanding, research in approaches to provide designers with the design information needed in a concise and straightforward way.

The workshop is of interest to practitioners working in circuit design and to researchers interested in design automation.

The aim of the 4th Workshop on Design Automation for Understanding Hardware Designs (DUHDe) is to consolidate the community for these topics in electronic design automation. The workshop is not limited to the following topics in design understanding but includes:

Program

Time Talk
08:30–08:35 Workshop Opening
Ian G. Harris and Mathias Soeken
08:35–09:35 Invited Talk 1: Reactive Program Synthesis and Repair

Speaker: Barbara Jobstmann, EPFL and Cadence Design Systems

Abstract: Reactive Synthesis aims to automatically construct a reactive program from a temporal specification that describes the desired functional behavior of the system. Often one does not need or want to construct a system from scratch but extend or repair a given system, which makes program repair an interesting alternative. In this talk I will first give a short introduction to Reactive Synthesis. Then, I will present an approach to repair reactive programs using reactive synthesis. This approach aims to produce for a repaired program that satisfies the specification and is syntactically close to the faulty program. Finally, I will present an extension of this approach that produces a program that is also semantically close to the original program by enforcing that a subset of the original traces is preserved. Intuitively, the faulty program is considered to be a part of the specification, which enables us to synthesize meaningful repairs, even for incomplete specifications.
09:35–10:00 ELVE: An Interactive and Extensible Visualisation Tool for Logic Circuits
Gregoire Hirt, Ana Petkovska, and Paolo Ienne
10:00–10:20 Coffee break
10:30–11:30 Invited Talk 2: When and how to automatically repair bugs?

Speaker: Martin Monperrus, University of Lille & INRIA

Abstract: I will talk about automatic repair of software bugs. I will describe the different use cases of automatic software repair, and the readiness level of each use case according to the latest advances of the research community. At the end of the talk, I will sketch the vision of "antifragile software", software that does not wait for bugs to naturally happen before doing something.
11:30–12:00 Mining Latency Guarantees for RT-level Designs
Jan Malburg, Heinz Riener, and Goerschwin Fey
12:00–13:00 Lunch
13:00–13:25 Verilog2GEXF Dynamic Large Scale Circuit Visualization
Kenneth Schmitz, Jannis Stoppe, and Rolf Drechsler
13:25–13:50 Computing Exact Fault Candidates Incrementally
Heinz Riener and Goerschwin Fey
13:50–14:15 A Human-Centered Approach to Routing for Digital Microfluidic Biochip
Oliver Keszocze, Andre Pols, and Rolf Drechsler
14:15–14:40 Making Waveforms Great Again
Jannis Stoppe and Rolf Drechsler
14:40–15:00 Coffee break
15:00–15:25 A Natural Language Interface to Design Cyber-Physical Systems
Sophia Balkovski and Ian Harris
15:25–15:50 On Identifying Functional Primitives in Hardware Description Language (HDL) Specifications
Christian Krieg, Martin Mosbeck, Clifford Wolf, and Axel Jantsch
15:50–16:00 Workshop Closing

Proceedings

The proceedings of DUHDe are only available for participants of the workshop.

Call for Papers and Submission Instructions

Prospective authors are requested to submit either an extended abstract 2-3 pages long, or a full paper 6 pages long. All submissions should be in IEEE two-column format. Authors of accepted contributions are required to present their work at the workshop. Authors have the option of submitting a full 6 page contribution for inclusion in the informal proceedings which will be distributed to participants of the workshop. Accepted papers will NOT be included in the DATE proceedings. The authors retain the copyright of their work and are free to submit extended versions to a conference or journal.

Please submit papers at the following site: https://easychair.org/conferences/?conf=duhde2017

Deadline for extended abstracts or full papers: November 10, 2016
Notification of acceptance: November 24, 2016
Camera ready papers: January 20, 2017

Registration

To be announced

Event Format

The workshop is organized as a Friday workshop associated to DATE 2017.

The topic of design understanding is relatively new as a research topic in hardware. The goal of the workshop is to solicit presentations that resemble early ideas or summarize existing work. The workshop includes the following invited speakers:

Committee

Organizers

Technical PC

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