Fall 2009

CS 153-Logic Design Laboratory

Instructor: Professor Eli Bozorgzadeh, Computer Science Department

Lecture Hours / Location: Mon-Wed-Fri  2:00-2:50 p.m. / DBH 1423

Lab Hours / Location: Mon-Wed 4:30-5:50 p.m. / ICS 192 (UCI Map: E6-Location #302)

Co-requisites:

ICS 151 or consent of the instructor.  Students should have familiarity with fundamentals of integrated circuit blocks.

Course Grading:

Projects (100%)- demo (70%), report (30%)

submit your report through EEE tool.

Resources

• ModelSim
• ModelSim Student Edition
• P.J. Ashenden, The VHDL Cookbook
• "VHDL for Digital Design", by Frank Vahid and Roman Lysecky, John Wiley and Sons Inc, 2006.

Lecture Topics

• Introduction to VHDL
• Combinational Circuits (example)
• Sequential Circuits

 Projects

[Note: Please provide your project demo to your TA during lab hours and submit your project report through EEE tool ]

Project 1 – Due Monday Oct 5, 2009

Project 2- Due Wednesday Oct 14,2009

Project 3- Due Wednesday Oct 21, 2009

Project 4- Due Monday Nov 2, 2009

Project 5- Due Monday Nov 23, 2009 (Click here for examples of sequential component design and FSM in VHDL.)

Project 6- Due Wednesday Dec 2, 2009