Project 6

Design a processor, in VHDL, that determines if a 8-bit unsigned value N is
prime or not. Your top-level entity should be similar to the following:

entity PRIME is
  port(clck     : in  STD_LOGIC;
       rst      : in  STD_LOGIC;
       N        : in  UNSIGNED(7 downto 0);
       is_prime : out STD_LOGIC;
       done     : out STD_LOGIC);
end PRIME;

Of course, your PRIME entity should in turn be decomposed into a controller
entity and a datapath entity. You may assume that the input N will not change
during the computation.

You need to also design a testbench and verify your design. There is no
requirement for your testbench to be exhaustive. However, for your demo, the
TA may provide any value for N and you have to be able to demonstrate the
operation of your div/mod entity.

Complete a report and attach to it all source VHDL files. Your report should
include your name, a description of the VHDL files attached, any special
notes or comments, and a description of how you tested your design. Also, your
report should contain the datapath drawing and controller FSM.

Your TA will provide you with information on tools, lab setup, and other things
related to this project. Make sure you seek help to get you started.