Publications

Book Chapters

BC4- Nga Dang, Elaheh Bozorgzadeh, Nalini Venkatasubramanian , “Energy Harvesting for Sustainable Smart Spaces”, Book chapter in Green Computing, edited by Ali Hurson, Advance in Computing, volume 47, Elsevier, 2012.

BC3- E. Bozorgzadeh, A. Kaplan, R. Kastner, S. Ogrenci Memik, and M. Sarrafzadeh, "Optimization for Reconfigurable Systems Using Hierarchical Abstraction", J. Cong and J. R. Shinnerl (Editors). Multilevel Optimization and VLSI CAD. Kluwer Academic Publishers, Boston, 2002.

BC2- X. Yang, E. Bozorgzadeh, M. Sarrafzadeh, and M. Wang, "Modern Standard-cell Placement Techniques". Layout Optimization in VLSI Design, Kluwer Academic Publishers, 2002.

BC1- E. Bozorgzadeh, R. Kastner, S. Ogrenci Memik, and M. Sarrafzadeh, "Strategically Programmable Systems ", The Computer Engineering Handbook, CRC Press, December 2001. 

Journal Papers

J21- M. Rahmatian, H. Kooti, Ian G. Harris and E. Bozorgzadeh, "Hardware-Assisted Detection of Malicious Software in Embedded Systems", IEEE Embedded Systems Letters (ESL), accepted for publication.

J20- Nga Dang, Elaheh Bozorgzadeh, Nalini Venkatasubramanian ,QuARES:Quality-aware Renewable Energy-driven Sensing Framework”, in Elseiver Sustainable Computing: Informatics and Systems Journal, 2012.

J19- Houman Homayoun, Shahin Golshan, Eli Bozorgzadeh, Alex Veidenbaum, Fadi Kurdahi, “On Leakage Power Optimization in Clock Tree Networks for ASICs and General-Purpose Processors, Elsevier Journal of Sustainable Computing: Information and Sciences, Volume 1, Issue 1, March 2011, Pages 75-87.

 J18-  Shahin Golshan, Hessam Kooti, Eli Bozorgzadeh , “SEU-aware High-level Data Path Synthesis and Layout Generation on SRAM-based FPGAs”, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol.30 (No.6), pp.829-840, 2011.

J17-  S. Banerjee, E. Bozorgzadeh, J Noguera, and N. Dutt, “Bandwidth Management in Application Mapping for Dynamically Reconfigurable Architectures”, in ACM Transactions on Reconfigurable Technology and Systems (TRETS),  pp. 1-30, Volume 3, No. 3, September 2010.

J16- S. Banerjee, E. Bozorgzadeh, and N. Dutt, "Exploiting application data-parallelism on dynamically reconfigurable architectures: placement and architectural considerations ", in  IEEE Transactions on VLSI (TVLSI), vol.17, no.2, pp.234-247, Feb. 2009.

J15- S. Oh, T. Kim, J. Cho and E. Bozorgzadeh, "Speculative Loop-Pipelining in Binary Translation for Hardware Acceleration", IEEE Transactions on CAD (TCAD),  pp. 409- 422, No. 3, Vol. 27, 2008.

J14- L. Singhal and E. Bozorgzadeh, "Multi-layer Floorplanning for Reconfigurable Designs", in IET Computers & Digital Techniques, pp. 276-294, No. 1, Vol. 4, 2007.

 J13-L. Singhal, E. Bozorgzadeh, and D. Eppstein, "Interconnect Criticality Driven Delay Relaxation", in IEEE Transactions on CAD (TCAD),pp.1803-1817, ,No. 10,  Vol. 26, 2007.

J12- S. Banerjee, E. Bozorgzadeh, N. Dutt, "Integrating physical constraints in HW-SW partitioning for architectures with partial dynamic reconfiguration", in IEEE Transactions on VLSI (TVLSI), Vol 14 (11), pp 1189-1202,  Nov 2006.

J11- S. Ghiasi, E. Bozorgzadeh, P. Huang, R. Jafari, and M. Sarrafzadeh, "A Unified Theory of Timing Budget Management",  in  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 25, No. 11, pp. 2364-2375, November 2006.

J10- S. Pasricha, N. Dutt, , E. Bozorgzadeh, M. Ben-Romdhane, " FABSYN: Floorplan-Aware Bus Architecture Synthesis", in IEEE Transactions on VLSI (TVLSI), pp. 241-253 ,Vol. 14, No. 3, 2006.

J9- G. Wang, S. Sivaswamy, C.  Ababei,  K. Bazargan, R. Kastner, and E. Bozorgzadeh, "Statistical Analysis and Design of HARP FPGAs",  in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), pp. 2088-2102, Vol. 25, No. 10, 2006.

J8- S. Ghiasi, K. Nguyen, E. Bozorgzadeh, M. Sarrafzadeh, "Efficient Timing Budget Management for Accuracy Improvement in a Collaborative Object Tracking System",  in  Journal of VLSI Signal Processing for Signal Processing and Video Technology, 42(1), pp. 43-55. 2006. 

J7- S. Ogrenci Memik, R. Kastner, E. Bozorgzadeh, and M. Sarrafzadeh, "A Scheduling Algorithm for Optimization and Early Planning in High level Synthesis",  ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 10, No. 1, pp. 33–57, January 2005.

J6- E. Bozorgzadeh, S. Ghiasi, A. Takahashi , and M. Sarrafzadeh, "Optimal Integer Delay Budget Assignment on Directed Acyclic Graphs", in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 23, No. 7,  pp. 1184- 1199 , August 2004.

J5- E. Bozrgzadeh, S. Ogrenci Memik, X. Yang, and M. Sarrafzadeh, "Routability-driven Packing : Metrics and Algorithms for Cluster-based FPGAs",  in  Journal of Circuits, Systems, and Computers (JCSC), Vol. 13, No. 1, pp. 77-100, Feb. 2004.

 J4- E. Bozorgzadeh, R. Kastner, and Majid Sarrafzadeh, "Creating and Exploiting Flexibility in Rectilinear Steiner Trees", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), pp.605-615, Vol. 22, No. 5, May 2003.

J3- R. Kastner, Adam Kaplan,  S. Ogrenci Memik, E. Bozorgzadeh, "Instruction Generation for Hybrid Reconfigurable Systems", ACM Transactions on Design Automation of Embedded Systems (TODAES), pp. 605-627, Vol.7, No. 4, October 2002.

J2- C. Chen, E. Bozorgzadeh, A. Srivastava, and Majid Sarrafzadeh, "Budget Management with Applications",  Algorithmica, Vol. 34, No. 3,  pp. 261-275, July 2002.

J1- R. Kastner, E. Bozorgzadeh, and M. Sarrafzadeh, "Pattern Routing: Use and Theory for Increasing Predictability and Avoiding Coupling", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), pp. 777-790, vol. 21, No. 7, July 2002

 

Conference Papers

C50- Mehryar Rahmatian, Hessam Kooti, Ian Harris and Elaheh Bozorgzadeh, “Minimization of Trojan Footprint by Reducing Delay and Area Impact “, in IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, October 2012.

C49- M. Rahmatian, H. Kooti, I. Harris and E. Bozorgzadeh, " Adaptable Intrusion Detection Using Partial Runtime Reconfiguration”, in 30th IEEE International Conference on Computer Design (ICCD’12), October 2012.

C48- H. Kooti, N. Dang, D. Mishra, E. Bozorgzadeh, "Energy Budget Management for Energy Harvesting Embedded Systems", in 18th IEEE International Conference on Embedded and Real-Time Computing System and Applications (RTCSA12), August 2012.

C47- D. Mishra, Y. Samei, N. Dang, R. Doemer, E. Bozorgzadeh,  Multi-layer Configuration Exploration of MPSoCs for Streaming Applications”, in Electronic System Level Synthesis Conference, San Francisco, California, June 2012.

C46- L. Singhal, H. Kooti and E. Bozorgzadeh, " Process Variation-aware Task Replication for Throughput Optimization in Configurable MPSoCs”, in 2012 Electronic System Level Synthesis Conference (ESLsyn12), June 2012.

C45- Shahin Golshan, Amin Khajeh, Houman Homayoun, Eli Bozorgzadeh, Ahmed M. Eltawil, Fadi J. Kurdahi: Reliability-aware placement in SRAM-based FPGA for voltage scaling realization in the presence of process variations. CODES+ISSS 2011: 257-266

C44- Nga Dang, Elaheh Bozorgzadeh, Nalini Venkatasubramanian ,QuARES: Quality-aware Data Collection in Energy Harvesting Sensor Networks”, 2nd Green Computing Conference (IGCC'11), July 25-28, 2011, Florida, USA.

C43- Shahin Golshan, Love Singhal, Eli Bozorgzadeh: Process variation aware system-level load assignment for total energy minimization using stochastic ordering. ISQED 2011: pp. 566-571.

C42- H. Kooti, D. Mishra and E. Bozorgzadeh,  "Reconfiguration-aware real time Scheduling under QoS Constraint", in 16th Asia and South Pacific Design Automation Conference (ASP-DAC11), January 2011.

C41- H. Kooti, E. Bozorgzadeh, "Unified Theory of Real-Time Task Scheduling and Dynamic Voltage/Frequency Scaling on MPSoCs", in ACM/IEEE  International Conference on Computer-Aided Design (ICCAD10), San Jose, November 2010.

C40- S. Golshan, E Bozorgzadeh, B. Carrión Schäfer, K. Wakabayashi, H. Homayoun, A.. Veidenbaum, “Exploiting power budgeting in thermal-aware dynamic placement for reconfigurable systems”, in IEEE   International Symposium on Low Power Electronics and Design (ISLPED), pp. 49-54, 2010.

C39- H. Homayoun, S. Golshan, E. Bozorgzadeh, Fadi Kurdahi, Alex Veidenbaum, Post-Synthesis Sleep Transistor Insertion for Leakage Power Optimization in Clock Tree Networks”, in 11th  IEEE International Symposium on Quality Electronic Design. (ISQED), pp. 499-507, 2010.

C38- H. Kooti, E. Bozorgzadeh, S. Liao and L. Bao, "Reconfiguration-aware Spectrum Sharing for FPGA based Software Defined Radio", in 17th Reconfigurable Architectures Workshop (RAW10), Atlanta, April 2010.

C37- H. Kooti, E. Bozorgzadeh, S. Liao and L. Bao, "Transition-aware Real-Time Task Scheduling for Reconfigurable Embedded Systems", in IEEE Design, Automation and Test in Europe (DATE10), Germany, pp. 232-237, March 2010

C36- L. Bao, S. Liao and E. Bozorgzadeh, "Spectrum Access Scheduling among Heterogeneous Wireless Systems", in Proc. of SDR Forum Technical Conference and Product Exposition (SDR), Washington, DC, 2009.

C35- S. Golshan, and E. Bozorgzadeh, "SEU-Aware Resource Binding for Modular Redundancy Based Designs on FPGAs", to appear in ACM/IEEE International Conference on Design, Automation, and Test in Europe (DATE), pp. 1124-1129, April 2009.

C34- L. Singhal and E. Bozorgzadeh, " Process Variation Aware System-level Task Allocation using Stochastic Ordering of Delay Distributions", in ACM/IEEE International Conference on Computer-Aided Design (ICCAD), pp. 570-574, November 2008.

C33- L. Singhal, S. Oh, and E. Bozorgzadeh, " Yield Maximization for System-level Task Assignment and Configuration Selection of Configurable Multiprocessors", in ACM/IEEE IEEE/ACM international Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pp. 249-254, October 2008.

C32. A. Gholamipour, E. Bozorgzadeh, and L. Bao, “Seamless Sequence of Software Defined Radio Designs through Hardware Reconfigurability of FPGAs”,  in IEEE International Conference on Computer Design (ICCD),pp. 260-265, October 2008.

C31-  L. Singhal, S. Oh, and E. Bozorgzadeh, "Statistical Power Profile Correlation for Realistic Thermal Estimation", in ACM/IEEE Asia-South Pacific Design Automation Conference (ASPDAC), pp. 67-70, January 2008.

C30- A. Gholamipour, E. Bozorgzadeh  and S. Banerjee, “Energy-aware Co-processor Selection for Embedded Processors on FPGAs”, in International Conference on Computer Design (ICCD), pp. 158-163, October 2007.

C29- L. Singhal and E. Bozorgzadeh, "Novel multi-layer floorplanning for Heterogeneous FPGAs", in IEEE International Conference on Field Programmable Logic and Applications (FPL), pp. 613-616,  August 2007.

C28- S. Golshan and E. Bozorgzadeh, "Single-Event-Upset Awareness in FPGA Routing", in Proc. of  ACM/IEEE Design Automation Conference (DAC), p. 330 – 333, June 2007.

C27- S. Banerjee, E. Bozorgzadeh, J Noguera, and N. Dutt, "Selective bandwidth and resource management in scheduling for dynamically reconfigurable architectures",  in Proc. of ACM/IEEE Design Automation Conference (DAC), pp. 771 – 776, June 2007.

C26- L. Singhal and E. Bozorgzadeh, "Heterogeneous Floorplanner for FPGA", in IEEE Field Programmable Custom Computing Machines (FCCM), pp. 311-312, April 2007.

C25-S. Banerjee, E. Bozorgzadeh, J. Noguera,  N. Dutt, "Minimizing Peak Power For Application Chains on Architectures with Partial Dynamic Reconfiguration", in International Conference on Field Programmable Technology (FPT), pp. 273 – 276,  December 2006.

C24- L. Singhal and E. Bozorgzadeh, "Multi-layer Floorplanning on a Sequence of Reconfigurable Designs", in IEEE International Conference on Field Programmable Logic and Applications (FPL), pp. 605-612,  2006. (received the best paper award)

C23- S. Dai and E. Bozorgzadeh, “CAD Tool for FPGAs with Embedded Hard Cores for Design Space Exploration of Future Architectures”,  in Proceedings of IEEE Symposium on Field-Programmable Custom Computing Machines, pp. 329-330, April 2006.

C22-L. Singhal, and E. Bozorgzadeh, "Physically-aware Exploitation of Component Reuse in Partially Reconfigurable Architectures”, in Proceedings of Parallel and Distributed Processing Symposium (IPDPS-RAW), Greece, April 2006.

 C21-S. Banerjee, E. Bozorgzadeh, and N. Dutt, "PARLGRAN: Parallelism Granularity Selection for Scheduling Task Chains on Dynamically Reconfigurable Architectures", in ACM/IEEE Asia-South Pacific Design Automation Conference (ASPDAC'01), pp.491-496 Japan, January 2006.

C20- L. Singhal and E. Bozorgzadeh, “Fast Timing Closure through Interconnect Criticality Driven Delay Relaxation", in ACM/IEEE International Conference on Computer-Aided Design (ICCAD), pp. 791-796, Nov. 2005.

C19- S. Banerjee, E. Bozorgzadeh, N. Dutt, "Physically-aware HW-SW Partitioning for reconfigurable architectures with partial dynamic reconfiguration", in ACM/IEEE Design Automation Conference (DAC), pp. 335 – 340, June 2005

C18- S. Pasricha, N. Dutt, , E. Bozorgzadeh, M. Ben-Romdhane, "Floorplan-aware Automated Synthesis of Bus-based Communication Architectures",  in ACM/IEEE Design Automation Conference (DAC), pp. 565- 570, June 2005. (nominated for best paper award)

C17-S. Banerjee, E. Bozorgzadeh, and N. Dutt, "Considering runtime reconfiguration overhead in Task Graph Transformations for dynamically reconfigurable architectures", in  IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM) , pp. 273- 274, Napa, April 2005

C16- S. Sivaswamy, G. Wang, C. Ababei, K. Bazargan, R.Kastner, and E. Bozorgzadeh, ”HARP:Hard-wired Routing Pattern FPGAs”, in Proceedings of  ACM International Symposium on Field-Programmable Gate Arrays (FPGA), pp. 21 – 29, Feb. 2005.

C15- S. Ghiasi, E. Bozorgzadeh, S.  Choudhuri, M. Sarrafzadeh, "A Unified Theory for Timing Budget Management", ACM/IEEE International Conference on Computer-Aided Design, pp. 653 – 659, Nov. 2004.

C14- E. Bozorgzadeh, S. Ghiasi, A. Takahashi, and M. Sarrafzadeh, "Incremental Timing Budget Management in Programmable Systems", International Conference on Embedded and Reconfigurable Systems and Architecture, pp. 240-246, July 2004.

C13- S. Ghiasi, K. Nguyen, E Bozorgzadeh, and M Sarrafzadeh, "On Computation and Resource Management in Networked Embedded Systems", International Conference on Parallel and Distributed Computing and Systems, pp. 445-451, November 2003.

C12- E. Bozorgzadeh, S. Ghiasi, A. Takahashi, and M. Sarrafzadeh, "Optimal Integer Delay Budgeting on Directed Acyclic Graphs",  ACM/IEEE Design Automation Conference (DAC'03) , pp. 920 - 925  ,2003.

C11- E. Bozorgzadeh, S. Ogrenci Memik, R. Kastner, and M. Sarrafzadeh, "Pattern Selection: Customized Block Allocation for Domain-Specific Programmable Systems", International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA'02), pp. 190-196,  June 2002.

C10- R. Kastner, S. Ogrenci Memik, E. Bozorgzadeh, and M. Sarrafzadeh, "Instruction Generation for Hybrid Reconfigurable Systems", ACM/IEEE International Conference on Computer-Aided Design (ICCAD'01), pp. 127-130, November, 2001.  

C9- S. Ogrenci Memik, E. Bozorgzadeh, R. Kastner, and M. Sarrafzadeh, "A Super-Scheduler for Embedded Reconfigurable Systems ", ACM/IEEE International Conference on Computer-Aided Design (ICCAD'01), pp. 391-394, November, 2001.  

C8- E. Bozorgzadeh, R.Kastner, and M. Sarrafzadeh, "Creating and Exploiting Flexibility in Steiner Trees", ACM/IEEE 38th Design Automation Conference (DAC'01), pp. 195 – 198, June 2001.

C7- S. Ogrenci Memik, E. Bozorgzadeh, R. Kastner, and M. Sarrafzadeh, "SPS: A Strategically Programmable System", Reconfigurable Architecture Workshop (RAW'01), April 2001.

C6- R. Kastner, E. Bozorgzadeh, and M. Sarrafzadeh, "An Exact Algorithm for Coupling-Free Routing", ACM/IEEE International Symposium on Physical Design (ISPD'01), pp. 10 – 15, April 2001.

C5- M. Sarrafzadeh, E. Bozorgzadeh, R. Kastner and A. Srivastava, "Design and Analysis of Physical Design Algorithms ", ACM/IEEE International Symposium on Physical Design (ISPD'01), pp. 82 – 89, April 2001.

C4- X.Yang, E. Bozorgzadeh, and M. Sarrafzadeh, "Wirelength and Rent exponents of Partitioning and Placement", ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP'01), pp. 25 – 31, April 2001.

C3- E. Bozorgzadeh, S. Ogrenci Memik,  andM. Sarrafzadeh, "RPack: Routability-Driven Packing for Cluster-Based FPGAs", Asia-South Pacific Design Automation Conference (ASPDAC'01), pp. 629 - 634, January 2001.

C2- R. Kastner, E. Bozorgzadeh, and M. Sarrafzadeh, "Predictable Routing", ACM/IEEE International Conference on Computer-Aided Design (ICCAD'00), pp. 110 – 114, November, 2000.

C1- R. Kastner, E. Bozorgzadeh, and M. Sarrafzadeh, "Coupling Aware Routing", IEEE International ASIC/SOC Conference, pp. 392-396, September 2000.