Publications

Elaheh Bozorgzadeh

[To view the publication list sorted by year of publications, please click here]

Book Chapters:

BC3- E. Bozorgzadeh, A. Kaplan, R. Kastner, S. Ogrenci Memik, and M. Sarrafzadeh, "Optimization for Reconfigurable Systems Using Hierarchical Abstraction", J. Cong and J. R. Shinnerl (Editors). Multilevel Optimization and VLSI CAD. Kluwer Academic Publishers, Boston, 2002.

 

BC2- X. Yang, E. Bozorgzadeh, M. Sarrafzadeh, and M. Wang, "Modern Standard-cell Placement Techniques". Layout Optimization in VLSI Design, Kluwer Academic Publishers, 2002.

 

BC1- E. Bozorgzadeh, R. Kastner, S. Ogrenci Memik, and M. Sarrafzadeh, "Strategically Programmable Systems ", The Computer Engineering Handbook, CRC Press, December 2001. 

Journals:

J18- [pending] L. Singhal, S. Oh, and  E. Bozorgzadeh, “Statistical Power Profile Correlation for Realistic Thermal-aware Floorplanning”, under revision for publication in ACM Transactions on Design Automation of Embedded Systems (TODAES).

 

J17- [pending] S. Banerjee, E. Bozorgzadeh, and N. Dutt, "Maximizing Performance with Limited Bandwidth and Logic Resources for Dynamically Reconfigurable Architectures", under revision for publication in ACM Transactions on Reconfigurable Technology and Systems (TRETS).

 

J16- S. Banerjee, E. Bozorgzadeh, and N. Dutt, "Exploiting application data-parallelism on dynamically reconfigurable architectures: placement and architectural considerations ", to appear in IEEE Transactions on VLSI (TVLSI).

 

J15- S. Oh, T. Kim, J. Cho and E. Bozorgzadeh, "Speculative Loop-Pipelining in Binary Translation for Hardware Acceleration", in  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 27, No. 3, pp. 409-423, March 2008.

 

J14- L. Singhal and E. Bozorgzadeh, "Multi-layer Floorplanning for Reconfigurable Designs",  IET Computers & Digital Techniques, No. 4, Vol. 1, pp.276-294, January 2007.

 

J13-  L. Singhal, E. Bozorgzadeh, and D. Eppstein, "Interconnect Criticality Driven Delay Relaxation",   in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 26, No. 10, pp. 1803-1817, October, 2007.

 

J12- S. Banerjee, E. Bozorgzadeh, N. Dutt, "Integrating physical constraints in HW-SW partitioning for architectures with partial dynamic reconfiguration",  in IEEE Transactions on VLSI (TVLSI), Vol 14 (11), pp 1189-1202,  Nov 2006.

 

J11- S. Ghiasi, E. Bozorgzadeh, P. Huang, R. Jafari, and  M. Sarrafzadeh, "Unified Theory of Timing Budget Management", in  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 25, No. 11, pp. 2364-2375, November 2006.

 

J10- G. Wang, S. Sivaswamy, C.  Ababei,  K. Bazargan, R. Kastner, and E. Bozorgzadeh, "Statistical Analysis and Design of HARP Routing Pattern FPGAs", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD),  pp. 2088-2102, Vol. 25, No. 10, 2006.

 

J9- S. Pasricha, N. Dutt, , E. Bozorgzadeh, M. Ben-Romdhane,"Floorplan-aware Automated Synthesis of Bus-based Communication Architectures", in IEEE Transactions on VLSI (TVLSI), pp. 241-253, Vol. 14, No. 3, March 2006.

 

J8- S. Ghiasi, K. Nguyen, E. Bozorgzadeh, M. Sarrafzadeh, "Efficient Timing Budget Management for Accuracy Improvement in a Collaborative Object Tracking System",  in Journal on Applied Signal Processing (EURASIP), Volume 42, Issue 1, Jan 2006, Pages 43 - 55. 

 

J7- S. Ogrenci Memik, R. Kastner, E. Bozorgzadeh, and M. Sarrafzadeh, "A Scheduling Algorithm for Optimization and Planning in High level Synthesis", ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 10, No. 1, Pages 33–57, January 2005.

 

J6- E. Bozorgzadeh, S. Ghiasi, and M. Sarrafzadeh, "Optimal Integer Delay Budget Assignment on Directed Acyclic Graphs", in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD),Vol. 23, No. 8, pp. 1184- 1199 , August 2004.

 

J5- E. Bozrgzadeh, S. Ogrenci Memik, X. Yang, and M. Sarrafzadeh,"Routability-driven Packing : Metrics and Algorithms for Cluster-based FPGAs",  in  Journal of Circuits, Systems, and Computers (JCSC), Vol. 13, No. 1, pp. 77-100, Feb. 2004.

 

 J4- E. Bozorgzadeh, R. Kastner, and Majid Sarrafzadeh,"Creating and Exploiting Flexibility in Rectilinear Steiner Trees", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), pp.605-615, Vol. 22, No. 5, May 2003.

 

J3- R. Kastner, Adam Kaplan,  S. Ogrenci Memik, E. Bozorgzadeh, "Instruction Generation for Hybrid Reconfigurable Systems", ACM Transactions on Design Automation of Embedded Systems (TODAES), pp. 605-627, Vol.7, No. 4, October 2002.

 

J2- C. Chen, E. Bozorgzadeh, A. Srivastava, and Majid Sarrafzadeh, "Budget Management with Applications",  Algorithmica, Vol. 34, No. 3,  pp. 261-275, July 2002.

 

J1- R. Kastner, E. Bozorgzadeh, and M. Sarrafzadeh, "Pattern Routing: Use and Theory for Increasing Predictability and Avoiding Coupling", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), pp. 777-790, vol. 21, No. 7, July 2002.

Conference Papers:

C34- L. Singhal and E. Bozorgzadeh, " Process Variation Aware System-level Task Allocation using Stochastic Ordering of Delay Distributions", to appear in ACM/IEEE International Conference on Computer-Aided Design (ICCAD), November 2008.

 

C33- L. Singhal, S. Oh, and E. Bozorgzadeh, " Yield Maximization for System-level Task Assignment and Configuration Selection of Configurable Multiprocessors", to appear in ACM/IEEE IEEE/ACM international Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), October 2008.

 

C32- A. Gholamipour, E. Bozorgzadeh and L. Bao, "Seamless Sequence of Software Defined Radio Designs through Hardware Reconfigurability of FPGAs", to appear in IEEE International Conference on Computer Design (ICCD), Oct.  2008.

 

C31-  L. Singhal, S. Oh, and E. Bozorgzadeh, "Statistical Power Profile Correlation for Realistic Thermal Estimation", in ACM/IEEE Asia-South Pacific Design Automation Conference (ASPDAC),

January 2008. 

 

C30- A. Gholamipour, S. Banerjee, and E. Bozorgzadeh, “Energy-aware Co-processor Selection for Embedded Processors on FPGAs”, in International Conference on Computer Design (ICCD), October 2007.

 

C29-  L. Singhal and E. Bozorgzadeh, "Novel multi-layer floorplanning for Heterogeneous FPGAs",  in IEEE International Conference on Field Programmable Logic and Applications (FPL), Amsterdam, August 2007.

 

C28- S. Golshan and E. Bozorgzadeh, "Single-Event-Upset Awareness in FPGA Routing",  in ACM/IEEE Design Automation Conference (DAC), 2007.

 

C27- S. Banerjee, E. Bozorgzadeh, J. Noguera, and N. Dutt, "Selective bandwidth and resource management in scheduling for dynamically reconfigurable architectures", in ACM/IEEE Design Automation Conference (DAC), 2007.

 

C26- L. Singhal and E. Bozorgzadeh, "Heterogeneous Floorplanner for FPGA", in IEEE Field Programmable Custom Computing Machines (FCCM), April 2007.

 

C25- S. Banerjee, E. Bozorgzadeh, J Noguera, and N. Dutt, "Minimizing Peak Power For Application Chains on Architectures with Partial Dynamic Reconfiguration", in International Conference on Field Programmable Technology (FPT), pp 273-276, December 2006.

 

C24- L. Singhal and E. Bozorgzadeh, "Multi-layer Floorplanning on a Sequence of Reconfigurable Designs",  in Proc. of IEEE International Conference on Field Programmable Logic and Applications (FPL), Madrid, Spain, August 2006. (FPL best paper award)

 

C23- S. Dai and E. Bozorgzadeh, “CAD Tool for FPGAs with Embedded Hard Cores for Design Space Exploration of Future Architectures”,  in Proc. of IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), April 2006.

 

C22-  L. Singhal and  E. Bozorgzadeh.“Physically-aware Exploitation of Component Reuse in Partially Reconfigurable Architectures”,  in 13th Reconfigurable Architectures Workshop (RAW'06), Greece, April 2006.

 

C21-S. Banerjee, E. Bozorgzadeh, and N. Dutt, "PARLGRAN: Parallelism Granularity Selection for Scheduling Task Chains on Dynamically Reconfigurable Architectures",  in ACM/IEEE Asia-South Pacific Design Automation Conference (ASPDAC'06), pp. 491-496,  Japan, January 2006.

 

C20- L. Singhal and E. Bozorgzadeh, “Fast Timing Closure through Interconnect Criticality Driven Delay Relaxation", in ACM/IEEE International Conference on Computer-Aided Design (ICCAD), Nov. 2005.

 

C19- S. Banerjee, E. Bozorgzadeh, N. Dutt, "Physically-aware HW-SW Partitioning for reconfigurable architectures with partial dynamic reconfiguration", in ACM/IEEE Design Automation Conference (DAC), June 2005. 

 

C18- S. Pasricha, N. Dutt, , E. Bozorgzadeh, M. Ben-Romdhane,"Floorplan-aware Automated Synthesis of Bus-based Communication Architectures",  in ACM/IEEE Design Automation Conference (DAC), June 2005. (nominated for best paper award)  

 

C17-S. Banerjee, E. Bozorgzadeh, and N. Dutt, "Considering runtime reconfiguration overhead in Task Graph Transformations for dynamically reconfigurable architectures", in  IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM) , pp. 273- 274 , April 2005.

 

C16- S. Sivaswamy, G. Wang, C. Ababei, K. Bazargan, R.Kastner, and E. Bozorgzadeh, ”HARP:Hard-wired Routing Pattern FPGAs”,  in Proceedings of  ACM International Symposium on Field-Programmable Gate Arrays (FPGA), Feb. 2005.

 

C15- S. Ghiasi, S.  Choudhuri, E. Bozorgzadeh, M. Sarrafzadeh, "A Unified Theory for Timing Budget Management", ACM/IEEE International Conference on Computer-Aided Design (ICCAD), Nov. 2004.

 

C14- E. Bozorgzadeh, S. Ghiasi, A. Takahashi, and M. Sarrafzadeh, "Incremental Timing Budget Management in Programmable Systems", International Conference on Embedded and Reconfigurable Systems and Architecture, July 2004. 

 

C13- S. Ghiasi, K. Nguyen, E Bozorgzadeh, and M Sarrafzadeh, "On Computation and Resource Management in Networked Embedded Systems", International Conference on Parallel and Distributed Computing and Systems, pp. 445-451, November 2003.

 

C12- E. Bozorgzadeh, S. Ghiasi, A. Takahashi, and M. Sarrafzadeh, "Optimal Integer Delay Budgeting on Directed Acyclic Graphs",  ACM/IEEE Design Automation Conference (DAC'03) , 2003. 

 

C11- E. Bozorgzadeh, S. Ogrenci Memik, R. Kastner, and M. Sarrafzadeh,"Pattern Selection: Customized Block Allocation for Domain-Specific Programmable Systems", International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA'02), June 2002.  

 

C10- R. Kastner, S. Ogrenci Memik, E. Bozorgzadeh, and M. Sarrafzadeh, "Instruction Generation for Hybrid Reconfigurable Systems", ACM/IEEE International Conference on Computer-Aided Design (ICCAD'01) , November, 2001.  

 

C9- S. Ogrenci Memik, E. Bozorgzadeh, R. Kastner, and M. Sarrafzadeh, "A Super-Scheduler for Embedded Reconfigurable Systems ", ACM/IEEE International Conference on Computer-Aided Design (ICCAD'01), November, 2001. 

 

C8- E. Bozorgzadeh, R.Kastner, and M. Sarrafzadeh, "Creating and Exploiting Flexibility in Steiner Trees", ACM/IEEE 38th Design Automation Conference (DAC'01), June 2001.  

 

C7- S. Ogrenci Memik, E. Bozorgzadeh, R. Kastner, and M. Sarrafzadeh, "SPS: A Strategically Programmable System", Reconfigurable Architecture Workshop (RAW'01), April 2001. 

 

C6- R. Kastner, E. Bozorgzadeh, and M. Sarrafzadeh, "An Exact Algorithm for Coupling-Free Routing", ACM/IEEE International Symposium on Physical Design (ISPD'01), April 2001.

 

C5- M. Sarrafzadeh, E. Bozorgzadeh, R. Kastner and A. Srivastava, "Design and Analysis of Physical Design Algorithms ", ACM/IEEE International Symposium on Physical Design (ISPD'01), April 2001. 

 

C4- X.Yang, E. Bozorgzadeh, and M. Sarrafzadeh, "Wirelength and Rent exponents of Partitioning and Placement", ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP'01), April 2001.

 

C3- E. Bozorgzadeh, S. Ogrenci Memik,  andM. Sarrafzadeh, "RPack: Routability-Driven Packing for Cluster-Based FPGAs", Asia-South Pacific Design Automation Conference (ASPDAC'01), Japan, January 2001.

 

C2-R. Kastner, E. Bozorgzadeh, and M. Sarrafzadeh, "Predictable Routing", ACM/IEEE International Conference on Computer-Aided Design (ICCAD'00), November, 2000.      

 

C1- R. Kastner, E. Bozorgzadeh, and M. Sarrafzadeh, "Coupling Aware Routing", IEEE International ASIC/SOC Conference, September 2000.


Poster Presentations (not appeared in the Proceedings)

P3- Soheil Ghiasi, Karlene Nguyen, Elaheh Bozorgzadeh, Majid Sarrafzadeh, "On Computation and Resource Management in an FPGA-based Computing Environment",  poster presentation at  ACM International Symposium on Field-Programmable Gate Arrays (FPGA'03), February 2003.

 

 P2- E.Bozorgzadeh and M. Sarrafzadeh, "Customized Regular Channel Design in FPGAs", poster presentation at ACM International Symposium on Filed-Programmable Gate Arrays (FPGA'03), February 2003.

 

 P1- E. Bozorgzadeh, S. Ogrenci Memik, R. Kastner, and M. Sarrafzadeh,"Pattern Selection in Programmable Systems", poster presentation at ACM International Symposium of Field Programmable Gate Arrays (FPGA'02), Feb. 2002.


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