Ian G. Harris

Associate Professor
University of California Irvine
Department of Computer Science
Email: harris at ics.uci.edu
Education: M.S., University of California San Diego , 1992, Ph.D., 1997.
B.S., Massachusetts Institute of Technology, 1990
  • Vice Chair of Graduate Studies

RESEARCH AREAS:

Go to the System Test Laboratory for details.

  • Hardware-Software Covalidation
  • Behavioral Design Validation
  • Testing of FPGA Architectures

    • COURSES:

    Freshman Seminar: How You Can Protect Yourself from Cyber-Attacks - Spring 2008
    CSE 181 Senior Design Project - Fall 2007, Winter 2008
    CS 151 Digital Logic Design - Summer Session 1 2007
    CS 153 Logic Design Laboratory - Spring 2007
    CS 151 Digital Logic Design - Summer Session 1 2006
    ICS 155B Computer Design Laboratory - Spring 2006

    SELECTED PUBLICATIONS:

  • I. G. Harris,
    "Covalidation of Complex Hardware/Software Systems" in System-on-Chip: Next Generation Electronics, Institution of Electrical Engineers Publishing (Bashir M. Al-Hashimi ed.), 2006.
  • M. Heath, W. Burleson, I. G. Harris,
    "Synchro-Tokens: A Deterministic GALS Methodology for Chip-Level Debug and Test" IEEE Transactions on Computers, vol. 54, num. 12, December 2005.
  • I. G. Harris,
    "Hardware/Software Covalidation" IEE Proceedings on Computers and Digital Techniques, vol. 152, num. 3, May 2005.
  • S. Verma, K. Ramineni, and I. G. Harris,
    "An Efficient Control-Oriented Coverage Metric" IEEE Asian South Pacific Design Automation Conference (ASPDAC), January 2005.
  • I. G. Harris
    "Tacking Concurrency and Timing Problems" in Test and Validation of Hardware/Software Systems Starting with System-Level Descriptions, Springer-Verlag Publishing (Matteo Sonza Reorda and Zebo Peng eds.), 2005.
  • M. Heath, W. Burleson, and I. G. Harris,
    "Eliminating Nondeterminism to Enable Chip-Level Test of Globally-Asynchronous Locally-Synchronous SoCs" IEEE/ACM Design Automation and Test in Europe (DATE) Conference, February 2004.