Ian G. Harris

Publications (since 1999)

• Ian G. Harris, "Capturing Assertions from Natural Language Descriptions", Workshop on Natural Language Analysis in Software Engineering (NaturaLiSE) , May 2013.
• Zi-Shun Huang and Ian G. Harris, "Return-Oriented Vulnerabilities in ARM Executables", to appear in Homeland Security Affairs Journal.
• M. Rahmatian, H. Kooti, Ian G. Harris and E. Bozorgzadeh, "Hardware-Assisted Detection of Malicious Software in Embedded Systems", IEEE Embedded Systems Letters (ESL), vol. 4, num. 4
• Ian G. Harris, "Generating Formal System Models from Natural Language Descriptions", IEEE High Level Design Validation and Test Workshop (HLDVT), November 2012.
• Best Paper Award , Zi-Shun Huang and Ian G. Harris, "Return-Oriented Vulnerabilities in ARM Executables", IEEE International Conference on Technologies for Homeland Security (HST), November 2012.
• M. Rahmatian, H. Kooti, Ian G. Harris and E. Bozorgzadeh, "Adaptable Intrusion Detection Using Partial Runtime Reconfiguration", IEEE International Conference on Computer Design (ICCD), October 2012.
• M. Rahmatian, H. Kooti, Ian G. Harris and E. Bozorgzadeh, "Minimization of Trojan Footprint by Reducing Delay and Area Impact", IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology (DFTS), October 2012.
• Ian G. Harris, "Extracting Design Information from Natural Language Specifications", IEEE/ACM Design Automation Conference (DAC), June 2012.
• Patricia S. Lee and Ian G. Harris, "Test Generation for Subtractive Specification Errors", IEEE VLSI Test Symposium (VTS), April 2012.
• Sharon Barner, Ian G. Harris, Daniel Kroening, and Orna Raz eds., "Hardware and Software: Verification and Testing, 6th International Haifa Verification Conference, HVC 2010 Haifa, Israel, October 2010 Revised Selected Papers, Lecture Notes in Computer Science", vol. 6504, Springer, 2010.
• Dhiraj K. Pradhan and Ian G. Harris eds., Practical Design Verification, Cambridge University Press, 2009
• S. Verma and Ian G. Harris, "SystemVerilog and Vera in a Verification Flow", in Practical Design Verification, Cambridge University Press, 2009
• Ian G. Harris and Dhiraj Pradhan eds. "Design Verification and Validation", Special Section of IEEE Transactions on VLSI Systems, April 2008.
• K. Ramineni, S. Verma, and I. G. Harris "Evaluation of an Efficient Control Oriented Coverage Metric", IEEE High Level Design Validation and Test Workshop, 2008.
• S. Verma, I. G. Harris, and K. Ramineni, "Automatic Generation of Functional Coverage Models from Behavioral Verilog Descriptions", IEEE/ACM Design Automation and Test in Europe (DATE) Conference, 2007.
• T. Alrahem, A. Chen, N. DiGiussepe, J. Gee, S.-P. Hsiao, S. Mattox, T. Park, A. Tam, I. G. Harris, and M. Carlsson, "INTERSTATE: A Stateful Protocol Fuzzer for SIP" , DEFCON 15, 2007.
• F. Fummi, I. G. Harris, C. Marconcini, and G. Pravadelli, "A CLP-based Functional ATPG for Extended FSMs", IEEE Microprocessor Test and Verification Workshop, 2007.
• K. Ramineni, I. G. Harris, and S. Verma, "Improving Feasible Interactions Among Multiple Processes", IEEE High Level Design Validation and Test Workshop, 2007.
• S. Verma, I. G. Harris, and K. Ramineni, "Automatic Generation of Functional Coverage Models from CTL", IEEE High Level Design Validation and Test Workshop, 2007.
• I. G. Harris, "Covalidation of Complex Hardware/Software Systems" System-on-Chip: Next Generation Electronics, Institution of Electrical Engineers Publishing (Bashir M. Al-Hashimi ed.), 2006.
• M. Heath, W. Burleson, I. G. Harris, "Synchro-Tokens: A Deterministic GALS Methodology for Chip-Level Debug and Test" , IEEE Transactions on Computers, vol. 54, num. 12, December 2005.
• I. G. Harris, "Hardware/Software Covalidation" , IEE Proceedings on Computers and Digital Techniques, vol. 152, num. 3, May 2005.
• S. Verma, K. Ramineni, and I. G. Harris, "An Efficient Control-Oriented Coverage Metric" , IEEE Asian South Pacific Design Automation Conference (ASPDAC), January 2005.
• I. G. Harris, "Tacking Concurrency and Timing Problems" Test and Validation of Hardware/Software Systems Starting with System-Level Descriptions, Springer-Verlag Publishing, Matteo Sonza Reorda and Zebo Peng eds., 2005.
• M. Heath, W. Burleson, and I. G. Harris, "Eliminating Nondeterminism to Enable Chip-Level Test of Globally-Asynchronous Locally-Synchronous SoCs" , IEEE/ACM Design Automation and Test in Europe (DATE) Conference, February 2004.
• E. Gaudette, M. Moussa, and I. G. Harris, "A Method for the Evaluation of Behavioral Fault Models" , IEEE High-Level Design, Validation, and Test Workshop (HLDVT), November 2003.
• D. A. Fernandes and I. G. Harris, "Application of Built in Self-Test for Interconnect Testing of FPGAs" , IEEE International Test Conference, September 2003.
• I. G. Harris, "Fault Models and Test Generation for Hardware-Software Covalidation", IEEE Design and Test of Computers, volume 20, number 4, July-August 2003.
• S. Arekapudi, F. Xin, J. Peng, I. G. Harris, "ATPG for Timing Errors in Globally Asynchronous Locally Synchronous Systems", Journal for Circuits, Systems and Computers, volume 12, number 3, June 2003.
• M. Heath and I. G. Harris "A Deterministic Globally Asynchronous Locally Synchronous Microprocessor Architecture", IEEE Microprocessor Test and Verification Workshop (MTV), May 2003.
• Z. Zeng, Q. Zhang, I. G. Harris, and M. Ciesielski, "Fast Computation of Data Correlation Using BDDs", IEEE/ACM Design Automation and Test in Europe (DATE) Conference, March 2003.
• Q. Zhang and I. G. Harris, "Partial BIST Insertion to Eliminate Data Correlation", IEEE Transactions on Computer-Aided Design, March 2003.
• I. G. Harris and R. Tessier, "Testing and Diagnosis of Interconnect Faults in Cluster-Based FPGA Architectures", IEEE Transactions on Computer-Aided Design, November 2002.
• F. Xin and I. G. Harris, "Test Generation for Hardware-Software Covalidation Using Non-Linear Programming", IEEE Workshop on High Level Design Validation and Test (HLDVT), October 2002.
• S. Arekapudi, F. Xin, J. Peng, I. G. Harris, "ATPG for Timing-Induced Functional Errors on Trigger Events in Hardware-Software Systems" , IEEE European Test Workshop (ETW), May 2002
• I. G. Harris, "Hardware-Software Covalidation: Fault Models and Test Generation", IEEE Workshop on High Level Design Validation and Test (HLDVT), November 2001
• S. Arekapudi, F. Xin, J. Peng, I. G. Harris, "Test Pattern Generation for Timing-Induced Errors in Hardware-Software Systems", IEEE Workshop on High Level Design Validation and Test (HLDVT), November 2001
• I. G. Harris, P. Menon, and R. Tessier, "BIST-Based Path Delay Testing in FPGA Arichitectures", IEEE International Test Conference (ITC), October 2001.
• Q. Zhang and I. G. Harris, "A Validation Fault Model for Timing-Induced Functional Errors", IEEE International Test Conference (ITC), October 2001.
• W. Burleson, A. Ganz, and I. G. Harris, "Educational Innovations in Multimedia Systems", ASEE Journal of Engineering Education, January 2001.
• Q. Zhang and I. G. Harris, "A Data Flow Coverage Metric For Validation of Behavioral HDL Descriptions", International Conference on Computer-Aided Design (ICCAD), 2000.
• I. G. Harris and R. Tessier, "Diagnosis of Interconnect Faults in Cluster-Based FPGA Architectures", International Conference on Computer-Aided Design (ICCAD), 2000.
• Q. Zhang and I. G. Harris, "A Domain Coverage Metric for the Validation of Behavioral VHDL Descriptions" , International Test Conference (ITC), October 2000.
• I. G. Harris and Russell Tessier, "Interconnect Testing of Cluster-based FPGA Architectures", Design Automation Conference (DAC), 2000.
• Q. Zhang and I. G. Harris, "Partial BIST Insertion to Eliminate Data Correlation", International Conference on Computer-Aided Design (ICCAD), 1999.
• Q. Zhang and I. G. Harris, "Mutation Analysis for the Evaluation of Functional Fault Models", High-Level Design, Validation, and Test Workshop (HLDVT), 1999.