Houman Homayoun Computing Innovation Fellow Department of Computer Science and Engineering University of California, San Diego Email: Phone: (949)-943-9639 ____________________________________________________________ Biographical Sketch Houman Homayoun is currently a 2010 National Science Foundation Computing Innovation Fellow (named by the Computing Research Association (CRA) and the Computing Community Consortium (CCC)).He is currently working with Professor Dean Tullsen at UC-San Diego. Houman Homayoun received the PhD degree from the department of computer science at the University of California Irvine in 2010, with Professors Alex Veidenbaum, Jean-Luc Gaudiot and Fadi Kurdahi. He was a recipient of the 4-years UC-Irvine computer science department chair fellowship. His dissertation was among the two out of 31 dissertations which were nominated by the computer science department for ACM doctoral dissertation award. His research is on power-performance temperature and reliability-aware memory and processor design optimizations and spans the areas of computer architecture, embedded systems and VLSI-CAD, where he has published more than 35 technical papers on the subject. His current research on CMP design is the first work presenting the new concept of dynamically heterogeneous processors leveraging 3D stacking technology. Houman Homayoun received his BS degree in electrical engineering in 2003 from Sharif University of technology, Tehran, Iran. He received his MS degree in computer engineering in 2005 from University of Victoria, Canada. ____________________________________________________________ HONORS & AWARDS 2010 2010 2006 2010 2009 2008 2006 2001 1998 ____________________________________________________________ Selected Publications [ISCA 2012] [HPCA 2012] [TVLSI 2012] [ISQED 2012] [TVLSI 2011] [TVLSI 2011] [TVLSI 2011] [CASES 2011] [CODES-ISSS 2011] [HiPEAC 2010] [ISLPED 2010] [CASES 2010] [DATE 2009] [CASES 2009] [CASES 2008] [DAC 2008] [ICCD 2008] [LCTES 2008] ____________________________________________________________ Service Technical Program Committee International Symposium on Low Power Electronics and Design (ISLPED-2012) IEEE International Symposium on Quality Electronic Design. (ISQED-2012) 2011 ACM International Conference on Computing Frontiers. (CF-2011) IEEE International Symposium on Quality Electronic Design. (ISQED-2011) Ninth IEEE International Conference on Computer Systems and Applications. (AICCSA-2011) Program Session Chair/Co-Chair The IEEE International Symposium on Quality Electronic Design. (ISQED-2011) The XXVI IEEE International Conference on Computer Design. (ICCD-2008) Reviewer 19th International Conference on Parallel Architectures and Compilation Techniques. (PACT-2010) ACM Transactions on Design Automation of Electronic Systems. (TODAES) The First International Green Computing Conference. (IGCC-2010) The 23rd International Conference on Supercomputing. (ICS-2009) International Conference on Compilers, Architecture, and Synthesis for Embedded Systems. (CASES-2009) International Symposium on Low Power Electronics and Design. (ISLPED-2009) The 35th International Symposium on Computer Architecture. (ISCA-2008) The XXVI IEEE International Conference on Computer Design. (ICCD-2008) The IEEE Transactions on COMPUTER-AIDED DESIGN of Integrated Circuits and Systems. (TCAD) The ACM International Conference on Computing Frontiers. (CF-2008) The IEEE Transactions on Very Large Scale Integration (VLSI) Systems. (TVLSI) International Symposium on Computer Architecture and High Performance Computing. (SBAC-PAD-2007) |
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- National Science Foundation CI Fellow Award, 280,000$. (two years)
Funded Project: Inter-core Selective Resource Pooling in a 3D Multicore.
ACM Doctoral Dissertation Award Nominee, UC-Irvine School of Information and
Computer Science Nominee (2 out of 31 dissertations selected).
4-Years Chair Fellowship Award, University of California Irvine,160,000$.
Computer Science Department.
Outstanding Graduate Student Award, (APSIH).
First Place, IEEE Orange County and Western Digital Student Design Contest.
8th International System-on-Chip Conference, Exhibit Workshops.
First Place, IEEE Orange County and Western Digital Student Design Contest.
7th International System-on-Chip Conference, Exhibit Workshops.
University Scholarship, McMaster University, Canada.
NAHAAL Scholarship for Excellence in Education and Research.
National Ranking, Rank 55 among more than 500,000 participants.
Iran Nationwide Universities Entrance Exam.
NEW!
Managing Distributed UPS Energy for Effective Power Capping in Data
Centers
Dynamically Heterogeneous Cores through 3D Resource Pooling.
Variation Trained Drowsy Cache (VTD-Cache): A History Trained
Variation Aware Drowsy Cache for Fine Grain Voltage Scaling
Hot Peripheral Thermal Management to Mitigate Cache Temperature
Variation.
MZZ-HVS: Multi Modes Zig-Zag Horizontal and Vertical Sleep Transistor
Sharing to Reduce Leakage Power in On-Chip SRAM Peripheral Circuits
Reducing Power in All Major CAM and SRAM Based Processor Units via
Centralized, Dynamic Resource Size Management
Inquisitive Defect Cache: A Means of Combating Manufacturing Induced
Process Variation
FFT-Cache: A Flexible Fault-Tolerant Cache Architecture for Ultra Low
Voltage Operation
Reliability-Aware Placement in SRAM-based FPGA for Voltage Scaling
Realization in the Presence of Process Variations
RELOCATE: Register File Local Access Pattern Redistribution
Mechanism for Power and Thermal Management in Out-of-Order
Embedded Processor
Exploiting Power Budgeting in Thermal-Aware Dynamic Placement for
Reconfigurable Systems
E < MC^2 : Less Energy through Multi-Copy Cache
Process Variation Aware Cache for Aggressive Voltage-Frequency
Scaling
Fault Tolerant Cache Architecture for Sub 500mv Operation
Multiple Sleep Mode Leakage Control for Cache Peripheral Circuits in
Embedded Processors
Dynamic Register File Resizing and Frequency Scaling to Improve
Embedded Processor Performance and Energy-Delay Efficiency
Adaptive Techniques for Leakage Power Management in L2 Cache
Peripheral Circuits
Improving Performance and Reducing Energy-Delay with Adaptive
Resource Resizing for Out-Of-Order Embedded Processors
Centers
Dynamically Heterogeneous Cores through 3D Resource Pooling.
Variation Trained Drowsy Cache (VTD-Cache): A History Trained
Variation Aware Drowsy Cache for Fine Grain Voltage Scaling
Hot Peripheral Thermal Management to Mitigate Cache Temperature
Variation.
MZZ-HVS: Multi Modes Zig-Zag Horizontal and Vertical Sleep Transistor
Sharing to Reduce Leakage Power in On-Chip SRAM Peripheral Circuits
Reducing Power in All Major CAM and SRAM Based Processor Units via
Centralized, Dynamic Resource Size Management
Inquisitive Defect Cache: A Means of Combating Manufacturing Induced
Process Variation
FFT-Cache: A Flexible Fault-Tolerant Cache Architecture for Ultra Low
Voltage Operation
Reliability-Aware Placement in SRAM-based FPGA for Voltage Scaling
Realization in the Presence of Process Variations
RELOCATE: Register File Local Access Pattern Redistribution
Mechanism for Power and Thermal Management in Out-of-Order
Embedded Processor
Exploiting Power Budgeting in Thermal-Aware Dynamic Placement for
Reconfigurable Systems
E < MC^2 : Less Energy through Multi-Copy Cache
Process Variation Aware Cache for Aggressive Voltage-Frequency
Scaling
Fault Tolerant Cache Architecture for Sub 500mv Operation
Multiple Sleep Mode Leakage Control for Cache Peripheral Circuits in
Embedded Processors
Dynamic Register File Resizing and Frequency Scaling to Improve
Embedded Processor Performance and Energy-Delay Efficiency
Adaptive Techniques for Leakage Power Management in L2 Cache
Peripheral Circuits
Improving Performance and Reducing Energy-Delay with Adaptive
Resource Resizing for Out-Of-Order Embedded Processors
