Hessam Kooti
	Ph.D. Computer Science Department University of California, Irvine
	3065 Bren Hall Computer Science Department University of California at Irvine Irvine, CA 92697-3435 USA	Email: hkooti@uci.edu web: http://ics.uci.edu/~hkooti
Research Interest:

• Reconfigurable Architectures
• Real-Time Scheduling
• Computer Aided Design
• Embedded Systems
• Software Defined Radio
• Application Specific Architecture

Education:

PhD in Computer Science, Sep. 2008 - Aug. 2012

Computer Science Department, University of California, Irvine

Supervisor: Professor Eli Bozorgzadeh

M.Sc. in Computer Hardware Engineering, Sep. 2006 - July 2008

Computer Engineering Department, Sharif University of Technology, Tehran, Iran

§ GPA (out of 20):    18.64

Thesis Title: "Evaluation of Power Consumption in Deadlock Recovery Routing Algorithms and improving Power-Delay Product (PDP)"

Supervisor: Professor Shaahin Hessabi

B.Sc. B.Sc. in Computer Hardware Engineering, Sep. 2001 - Feb. 2006

Computer Engineering Department, Sharif University of Technology, Tehran, Iran

§ GPA (out of 20):    15.64

Thesis Title: "Floating-Point Adder with Stored Unibit Transfer (SUT): A Study of Delay and Area"

Supervisor: Professor Ghasem Jaberipour

Publication:

Journal

• S.Golshan, H. Kooti and E. Bozorgzadeh, "SEU-aware High-level Data Path Synthesis and Layout Generation on SRAM-based FPGAs”,

in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 30, no 6, pp. 829 – 840, June 2011

Conference

• M. Rahmatian, H. Kooti, I. Harris and E. Bozorgzadeh, "Adaptable Intrusion Detection Using Partial Runtime Reconfiguration",

in 30th IEEE International Conference on Computer Design (ICCD12), Canada, 2012.

o L. Singhal, H. Kooti and E. Bozorgzadeh, " Process Variation-aware Task Replication for Throughput Optimization in Configurable MPSoCs ",

in 2012 Electronic System Level Synthesis Conference (ESLsyn12), San Francisco, 2012.

• H. Kooti, N. Dang, D. Mishra, E. Bozorgzadeh, "Energy Budget Management for Energy Harvesting Embedded Systems",

in 18th IEEE International Conference on Embedded and Real-Time Computing System and Applications (RTCSA12), Korea, 2012

• H. Kooti, D. Mishra and E. Bozorgzadeh, "Reconfiguration-aware Real-Time Scheduling under QoS Constraint",

in 16th Asia and South Pacific Design Automation Conference (ASP-DAC11), Japan, January 2011

• H. Kooti, E. Bozorgzadeh, "Unified Theory of Real-Time Task Scheduling and Dynamic Voltage/Frequency Scaling on MPSoCs",

in IEEE International Conference on Computer-Aided Design (ICCAD10), San Jose, November 2010

• H. Kooti, E. Bozorgzadeh, S. Liao and L. Bao, "Reconfiguration-aware Spectrum Sharing for FPGA based Software Defined Radio",

in 17th Reconfigurable Architectures Workshop (RAW10), Atlanta, April 2010

• H. Kooti, E. Bozorgzadeh, S. Liao and L. Bao, "Transition-aware Real-Time Task Scheduling for Reconfigurable Embedded Systems",

in IEEE Design, Automation and Test in Europe (DATE10), Germany, March 2010

• H. Kooti, M. Mirza-Aghatabar, A. Tavakkol, S. Hessabi, "Energy Analysis of Re-Injection Based Deadlock Recovery Routing Algorithms,"

in 10th International Symposium on System-on-Chip (SOC08), Finland, November 2008

Honors and Awards:

• ICS Fellowship for 3 years of support from UCI
• Outstanding Graduate Student Award, APSIH 2012
• Ranked 1^st among more than 300,000 participants in the national university entrance exam for M.Sc. degree
• Ranked 1^st among M.Sc. students of Computer Architecture major (Sharif Univ. of Tech.)
• Ranked 187^th among more than 350,000 participants in the national university entrance exam (Konkoor)

Experiences:

o Graduate Student Researcher 2008-2012

The focus of my research is on FPGA SoCs. I am currently working on implementing Software Defined Radio on FPGAs. This project needs research in various aspects of dynamic partial reconfiguration on FPGAs, Real-time Scheduling and also knowledge about wireless communication protocols. The goal of my research is to provide tool support to bridge the gap between physical layer and networking layer of an SDR application by providing efficient reconfiguration scheme. At the same time the tool should provide necessary information about the physical layer to the networking layer to help it during spectrum access scheduling. This work mostly includes ILP programming and C# coding. My current project is implementing LEON3 processor along with a new hardware-based intrusion detection technique on a Xilinx FPGA and loading Linux OS on the processor. The goal of the project is detecting the intrusion attacks at running codes on the processor and partial reconfiguring the hardware detection part on FPGA to adapt to running software.

o STEC SSD Company – Test Engineering Intern 2011 (6 Months)

I worked in the DVT (Design, Verification and Test) group of the STEC Company. My main job was developing test tools and proposing new tests for checking the functionality of SSD drives. I used C# coding for developing the test software environment and python coding for developing the test scripts both on Windows and Linux platforms. I also developed the required projects in C++ for Windows and Linux for communicating with the drives.

o Research Assistant in NoC and Reconfigurable Computing Lab 2006-2008

I was involved in research on Routing Algorithms in NoC. My project was measuring the power and energy consumption of Deadlock Recovery and Deadlock Avoidance Routing Algorithms in realistic conditions. I also design two new methods for improving energy in Deadlock Recovery Routing Algorithms.

o Fannavari Moje Novin Co. 2005-2006

I worked with several communication protocols to communicate with various hardware including GPIB protocol to read data from a Spectrum. I also worked with serial communication to program a Synthesizer and read data from a GPS card. The other work I have done was creating a client-server communication application between several computers to update specific data with each other using Ethernet protocol using C#. Another part of my job was converting MATLAB codes for DSP processing algorithms to C# codes.

o Teaching Assistant

Sharif University of Technology

TA for "Microprocessors", "Hardware Description Languages", "Probability and Statistics", "Theory of Machines and Languages" and "Instructor of Digital Logic Design Lab".

University of California, Irvine

TA for "Digital Logic Design" and "Advanced Computer Architecture"

Technical Skills:

• Programming Languages: Java, C#, C++, Assembly
• Hardware Languages: VHDL, Verilog
• Operating Systems: Windows, Linux
• CAD Tools: Modelsim, ORCAD, PSPICE, MaxPlus, Leonardo, MATLAB

Accomplished Academic Projects:

• Floating-Point Adder with Stored Unibit Transfer (SUT): A Study of Delay and Area

(B.Sc. thesis) Professor Ghasem Jaberipour

In this project operands were in SUT representation and the proposed adder had no carry propagation. I implemented this adder in VHDL and analyzed its delay with simulation. Numbers of gates of this adder were also counted to have an estimation for its area.

• Stochastic Multicast Wormhole Routing on NoC

I implemented stochastic routing on NoC proposed by P. Bogdan et al "Stochastic Communication: A New Paradigm for Fault-Tolerant Networks-on-Chip", VLSI Design 2007. I improved the algorithm by employing wormhole switching and adding adaptively to the routing technique and changing the probability of each link to reduce power consumption and increase performance.

Resume

Sfcave (Game)