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PUBLICATIONS Ph.D. Dissertation |
"Multiprocessor System-on-Chip Data Memory Customization
for Embedded Array-Intensive Applications" |
| Conferences |
"Compiler Driven Data Layout Optimization for Regular/Irregular
Array Access Patterns" "A Compiler-in-the-Loop Framework to Explore Horizontally
Partitioned Cache Architectures" "Software controlled memory layout reorganization for irregular
array access patterns" "Data Reuse Driven Memory and Network-on-Chip Co-Synthesis" "Data Reuse Driven Energy-Aware MPSoC Co-Synthesis of Memory
and Communication Architecture for Streaming Applications" "Mitigating Soft Error Failures for Multimedia Applications
by Selective Data Protection" "Multiprocessor System-on-Chip Data Reuse Analysis for
Exploring Customized Memory Hierarchies" "Compilation techniques for energy reduction in horizontally
partitioned cache architectures" "FORAY-GEN: Automatic Generation of Affine Functions for
Memory Optimizations" "Data Reuse Analysis Technique for Software-Controlled
Memory Hierarchies" "Profile-based Dynamic Voltage Scheduling using Program Checkpoints" |
| Journals |
"Partially Protected Caches to Reduce Failures due to
Soft Errors in Multimedia Applications" "Adaptive Scratch Pad Memory Management for Dynamic
Behavior of Multimedia Applications" "Compiler-in-the-Loop Design Space Exploration Framework
for Energy Reduction in Horizontally Partitioned Cache Architectures" "Data Reuse Driven Energy-Aware Co-Synthesis of Scratch
Pad Memory and Hierarchical Bus Based Communication Architecture
for Multiprocessor Streaming Applications" "Using FORAY Models to Enable MPSoC Memory Optimizations" "DRDU: A Data Reuse Analysis Technique for Efficient Scratch
Pad Memory Management" |
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