Jelena Trajkovic

I received a PhD from the School of Information and Computer Sciences at the University of California, Irvine. My advisors are Prof. Dainel Gajski and Prof. Alex Veidenbaum. I am afiliated with the Center for Embedded Computer Systems.

I am currently a Post-Doctoral Researcher at Ecole Polytechnique de Montreal.

Research

I currently work on modeling and optimization of heterogeneous 3D MPSoC architectures, focusing on integration of optical networks-on-chip (ONoC). My work was supported by ReSMiQ Post-Doctoral Fellowship for 2010.

As a part of my PhD I worked on the No Instruction Set Computer (NISC) project. I designed and implemented algorithms that extract an optimal datapath architecture from given C code. My PhD work was supported by Graduate Dean's Dissertation Fellowship in Fall 2008.

I am also interested in memory heirerchy architecture. I designed reconfigurable memory controller for reducing energy consumption of main memory by combining read and/or write memory access.

Publications

Journal Papers:

J3 - J. Trajkovic, D. Gajski 'Automated Generation of Custom Processor Core from C Code,' To Applear in Journal of Electrical and Computer Engineering (March 2012)

J2 - S. Le Beux, J. Trajkovic, I. O'Connor, G. Nicolescu, G. Bois and P. Paulin 'Multi- Optical Network on Chip for Large Scale MPSoC,' In IEEE Embedded Systems Letters (Vol. 2, Issue 3, Pages 77 - 80) (Sept. 2010) (pdf)

J1 - J. Trajkovic, A. Veidenbaum, A. Kejariwal 'Improving SDRAM Access Energy Efficiency for Low-Power Embedded Systems,' In ACM Transactions on Embedded Computing Systems (Volume 7 , Issue 3 (April 2008); Article No. 24; Year of Publication: 2008; ISSN:1539-9087) (April 2008) (pdf)

Conference Papers:

C8 - S. Le Beux, J. Trajkovic, I. O'Connor, and G. Nicolescu 'Layout Guidelines for 3D Architectures including Optical Ring Network-on-Chip (ORNoC),' Referred Invited Paper, In Proceedings of 19th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SOC), Kowloon, Hong Kong (Oct. 2011) (pdf)

C7 - S Le Beux, J. Trajkovic, G Nicolescu, G Bois, I O'Connor, and P. Paulin 'Optical Ring Network-on-Chip (ORNOC). Architecture and Design Methodology,' In Proceedings of IEEE Design Automation and Test in Europe, March 2011 (pdf)

C6 - J. Trajkovic, and D. Gajski 'Early Performance-Cost Estimation of Application-Specific Data Path Pipelining,' In Proceedings of Eighth IEEE Symposium on Application Specific Processors (SASP), Anaheim, California (June 2010) (pdf) (slides)

C5 - J. Trajkovic, D. Gajski, A. Veidenbaum 'Application Specific Processor Core Construction from C Code,' In ACM/SIGDA PhD Forum, Design Automation Conference, Anaheim, California (June 2008) (pdf)

C4 - J. Trajkovic, D. Gajski 'Custom Processor Core Construction from C Code,' In Proceedings of Sixth IEEE Symposium on Application Specific Processors, Anaheim, California (June 2008) (pdf) (slides)

C3 - J. Trajkovic, and D. Gajski 'Automatic Data Path Generation from C code for Custom Processors,' Best Paper Award, In Proceedings of International Embedded Systems Symposium 2007, IFIP International Federation for Information Processing, Volume 231, Embedded System Design: Topics, Techniques and Trends (ed. A. Rottenberg, M. Zanella, R. Dömer, A. Gerstlauer, F. Ramming), Springer, Irivne, USA (June 2007) (pdf) (slides)

C2 - J. Trajkovic, and D. Gajski 'Automatic Architecture Selection for Custom Processors,' In Proceedings of SRC Student Symposium (Oct. 2006) (pdf) (slides) (poster)

C1 - J. Trajkovic, M. Reshadi, B. Gorjiara, and D. Gajski 'A Graph Based Algorithm for Data Path Optimization in Custom Processors,' In Proceedings of 9th Euromicro Conference on Digital System Design (Sept. 2006) (pdf) (ppt slides)

BookChapters:

B1 - S. Le Beux, J. Trajkovic, I. O'Connor, G. Nicolescu, , G. Bois, and P. Paulin 'System Level Exploration for Optical Interconnect Architectures,' In book (Integrated Optical Interconnect Architecures for Embedded Systems (Springer) (To Appear in 2012)

Technical Reports:

TR3 - J. Trajkovic, D. Gajski 'Generation of Custom Co-processor Structure from C-Code,' CECS- TR-08-05, University of California, Irvine (June 2008) (pdf)

TR2 - J. Trajkovic, D. Gajski 'Communication Design for No Instruction Set Computer,' CECS- TR-05-09, University of California, Irvine (July 2005) (pdf)

TR1 - J. Trajkovic, A. Veidenbaum 'Reducing SDRAM Energy Consumption in Embedded Systems,' CECS-TR-04-02, University of California, Irvine (Mar. 2004) (pdf)

Thesis:

T2 - J. Trajkovic 'Automatic Design and Optimization of Application Specific Processors,' PhD Thesis, University of California, Irvine (March 2009)

T1 - J. Trajkovic 'Performance evaluation by simulation of simplified decoder for BCH code that corrects up to 4 errors,' Diploma Thesis, University of Belgrade (Sept. 2000)

Contact

Email:           j e l e n a t (at) c e c s. u c i. e d u   /or/
                     j e l e n a . t r a j k o v i c (at) p o l y m t l . c a

Personal

My favorite book: The Little Prince
Things I like to do: yoga, scuba diving, reading, swimming, hiking...
Photos: Cavtat and Dubrovnik
Some recipes from Goca T. and others ->
Fun place to go to is Color Me Mine, although I have not been there for a while...
Fingerprints music store in Long Beach

 
Last update on: Sept 2011