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VHDL Reference Guide - Constant Declaration
Constant Declaration

Declaration ---- used in ----> Entity


constant constant_name : type := value;
See LRM section

Rules and Examples

constant BUS_WIDTH : integer := 8;
constant FOUR_ONES :
       std_logic_vector(3 downto 0):= "1111";

constant PERIOD : time := 10 ns;
constant MAX_SIM_TIME : time:= 50 * PERIOD;
The values of array constants of types other than stribg, bit_vector and std_logic_vector, must be set using aggregates.
type T_CLOCK_TIME is ARRAY(3 downto 0) of
    integer range 0 to 9;
constant TWELVE_O_CLOCK :
    T_CLOCK_TIME := (1,2,0,0);
In a package, a constant may be deferred. This means its value is defined in the package body. the value may be changed by re-analysing only the package body.
package P is
  constant C : integer;
end P;

package body P is
  constant C : integer := 200;
end P;
Provided they are of the correct type, constants may be used in any expression. They may be associated with generics of component instances and passed into procedures.
  type T_DATA is array (0 to 3)
        of bit_vector(7 downto 0);
  constant DATA : T_DATA :=
  for I in DATA'range loop
  end loop;
end process;

Synthesis Issues

Constants are supported for synthesis, providing they are of a type acceptable to the logic synthesis tool. They are either synthesised as connections to logic '1' or '0', or are used to help minimise the number of gatyes required. Deferred constants may not bwe supported.

Whats New in '93

Constants and constant expressions may also be associated with input ports of component instances in VHDL-93. In VHDL-87 this was only possible via an intermediate signal.