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VHDL Reference Guide - Literals

Literal ---- used in ----> Expression


See LRM sections 7.3.1, 13.4, 3.1.1 and 3.1.3

Rules and Examples

Numeric literals with a decimal point are real, those without are integer;
constant FREEZE : integer := 32;
constant TEMP : real := 32.0;

Numeric literasls may be expressed in any base from 2 to 16. They may also be broken up using underscore, for clarity.
A_INT <= 16#FF#;
B_INT <= 2#1010_1010#;
MONEY := 1_000_000.0;

Real numbers may be expressed in exponential form:
FACTOR := 2.2E-6;

Literals of type time (and other physical types) must have units. The units should be preceded by a space, although some tools may not require this:
constant DEL1 :time := 10 ns;
constant DEL2 :time := 2.27 us;

Literals of enumerated types may either be characters (as for bit and std_logic), or identifiers:
type MY_LOGIC is ('X','0','1','Z');
signal CLK : MY_LOGIC := '0';
signal STATE : T_STATE := IDLE;

Literals for arrays of characters, such as string, bit_vector and std_logic_vector are placed in double quotes:
constant FLAG :bit_vector(0 to 7) := "11111111";
constant MSG : string := "Hello";

Bit vector literals may be expressed in binary (the default), opctal or hex. They may also contain embedded underscores for clarity. these forms may not be used as std_logic_vector literals:
BIT_8_BUS <= B"1111_1111";
BIT_9_BUS <= O"353";
BIT_16_BUS <= X"AA55";

For how to define other array literals and record literals, see arrays and .

non-printing characters may be included in a string literal using concatenation:
constant TWO_LINE_MSG : string := "Hello" & CR & "World";

Synthesis Issues

Literals are supported for synthesis, providing they are of a type acceptable to the logic synthesis tool. They are either synthesised as connections to logic '1' or '0', or are used to help minimised the number of gates required.

Whats New in '93

In VHDL-93, the pre-defined types character and string support an extended character set, including those used in most European languages.