Dynamic reconfiguration refers to reconfiguring a part of or full FPGA while the FPGA is running in field.
Reconfiguring only a part of FPGA is called Partial Reconfiguration. The field of partial dynamic reconfiguration
is new and has immense potential with the increasing popularity of FPGA. Though, the support of partial dynamic
reconfiguration (PDR) in current FPGAs is limited with only Xilinx Virtex and Spartan devices supporting
partial reconfiguration, the support for PDR is going to change with increasing device (re)configuration
speed, and architecture advancement. Even though, current architectures like Virtex 4 support
partial dynamic reconfiguration,
the software support for doing reconfiguration is very limited. Only recently, Xilinx has come up with a comprehensive
support for runtime reconfiguration in newer FPGAs. Still the high level design tasks for reconfiguration remain
unclear and the exact tradeoffs between runtime reconfiguration and larger designs have to be found.
This project aims at development of better tools
that optimize the reconfiguration aspect of FPGAs. I developed a floorplanning tool for runtime reconfiguration that
minimizes the reconfiguration overhead by reusing common components in the design. This work will be presented in RAW paper. More
optimal ways to reduce reconfiguration overheads are being studied.
Design Optimization using Budget Management
I am working
towards optimizing the parameters of design like speed, area and power by
using delay budget management techniques. The designs that I am currently
looking are mapped to FPGA.
The budget management techniques were studied by my advisor, Prof. Elaheh Bozorgzadeh, in her
doctorate thesis. These techniques consist of generic algorithms that
improve the additional slack on design components. Currently, I am trying
to improve the technique using new algorithms that manage critical paths.
Managing critical paths optimizes the design predictability and achieves
design closure.