NISC Technology Toolset (C-to-RTL) Datapath Generator / Selector Generates/Selects datapath for a given application Converts C => GNR (Generic Netlist Representation of datapath) NISC Cycle-accurate Compiler Compiles the application for a given datapath Converts C => CW (Control Words stream controlling components in each clock cycle) RTL Generator Generates the RTL for input to FPGA or ASIC Converts GNR+CW => RTL Datapath Refinement Refine datapath to improve quality Code Refinement Refine application to improve quality

NISC Technology Design Flow

In NISC Technology, the designer can iteratively refine to get satisfactory results.

• Architecture selection:
  • It can be selected from a set of pre-designed templates optimized for a specific application domain.
  • A customized architecture can be generated for a specific application by specifying netlist of components after profiling and analyzing the application.
• Compilation: The compiler maps the input C code on the given architecture.
• RTL generation: RTL generator translates the NISC netlist and the output of the compiler into synthesizable RTL.
• Synthesis: The final result can be simulated and synthesized for final implementation on FPGA or ASIC.
• Refinement: After analysis, application and/or architecture can be redefined until the desired results are achieved.

NISC Technology Strengths

• Both top-down and bottom-up design flow
  • Standard behavioral synthesis (a.k.a. high-level synthesis or HLS) tools provide only a top-down design flow (from high-level C to low-level RTL).
  • ASIP approaches provide only a bottom-up design flow (from custom-instructions up to using them in the application).
  • NISC provides both top-down flow (by generating architecture from C) and bottom-up flow (by providing datapath as input).
• Fast & Predictable path to implementation
• When using behavioral synthesis, a change in the application will result in many changes in the generated RTL. There is no way to predict or correlate the application changes to the changes in the results. Therefore the only way to improve unsatisfactory results is by trial-and-error and guesswork.
• When using ASIP, after adding a new custom instruction, the designer should either use HLS to synthesis the datapath and controller (unpredictable results), or must do it manually (very time consuming).
• NISC enables the designers to control every aspect of the design. The designer can select the exact points for improvement and then do it quickly. For example, by directly changing the GNR description of architecture, the designer can reduce a critical path delay or fix complex multiplexers and connections that consume too much power or make the layout unroutable.
• Designer-controlled design space exploration
• Since other tools and techniques do not provide fast & predictable path to implementation, the designer can at best explore the design aspects that the tool provides but not the ones the designer wants!
• Since datapath can be an input in NISC Technology, the designer can explore options for quality metrics selectively. For example, a designer can focus on dynamic power minimization by modifying the connections or gating or latching them in the datapath description and quickly see the effect on the final results.
• Right mixture of standard languages
  • Since ANSI C alone is not enough for designing a complete system, all HLS tools provide their own extension of C as input language. Such extensions require extra effort for learning. Additionally, they prevent the use of unmodified C code and lock the designer into a proprietary tool by making the developed algorithms unusable to other tools.
  • NISC Technology only uses standard languages. The designers do not need extra training and can use their favorite development tools such as editors and debuggers. NISC provides a seamless way of combining standard C and Verilog through pre-bound functions enabling the inclusion of low-level Verilog code inside a C program.