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	Nodari Sitchinava Assistant Professor University of Hawaii, Manoa Department of Information and Computer Sciences 1680 East West Road, POST 306B Honolulu, HI 96822
	Phone:	+1 (808) 956-3581
	Fax:	+1 (808) 956-3548
	Email:	nodari @ hawaii . edu

Research

I am interested in the design and analysis of algorithms, in particular, for multi-core architectures, external memory model, cache-oblivious model, and their parallel extensions, theoretical aspects of GPGPU computing and MapReduce framework. I am also interested in computational geometry and graph algorithms.

Prospective students: I am looking for bright and self-motivated students to work with on the topics in parallel, sequential, I/O-efficient and cache-oblivious algorithms and data structures with applications to high-performance computing. If you have strong theoretical or programming background and would like to work on algorithms and/or applications for multicores, GPUs and clusters of processors, take a look at my papers and apply to the graduate program at the University of Hawaii (information can be found here). Once you are admitted, drop me a line to discuss projects which might be of mutual interest.

Curriculum Vitae

Postscript version
PDF version

Teaching

ICS 491: Parallel Algorithms (Spring 2014)

Past Teaching

Algorithms for memory hierarchies (Winter 2012/2013) at KIT

Seminar on algorithms for realistic parallel models (Summer 2012) at KIT

I/O-efficient graph algorithms (Spring 2010) at MADALGO

Summer school on cache-oblivious algorithms (Summer 2008) at MADALGO

Committee Service

Sixth Workshop on Massive Data Algorithmics (MASSIVE), Wrocław, Poland, 2014, PC Chair

26th ACM Symposium on Parallelism in Algorithms and Architectures (SPAA), Prague, Czech Republic, 2014, PC member

Meeting on Algorithm Engineering & Experiments (ALENEX), Portland, OR, USA, 2014, PC member

5th Workshop on Massive Data Algorithmics (MASSIVE), Sophia Antipolis, France, 2013, PC member

24th Annual Symposium on Combinatorial Pattern Matching (CPM), Bad Herrenalb, Germany, 2013, OC member

Publications

All publications are in the alphabetical author order, except when marked with (*). You can also find my publications on Google Scholar and on DBLP.

Theses

N. Sitchinava "Parallel external memory model and algorithms for multicore architectures", Ph.D. Thesis, University of California, Irvine, September 2009.
N. Sitchinava "Dynamic scan chains — a novel architecture to lower the cost of VLSI test", Master Thesis, Massachusetts Institute of Technology, September 2003.

Conference Proceedings

R. Jakob, T. Lieber, N. Sitchinava. "On the complexity of list ranking in the parallel external memory model", in Proceedings of the 39th International Symposium on Mathematical Foundations of Computer Science (MFCS), 2014, to appear.
P. Afshani, N. Sitchinava. "I/O-efficient range minima queries", in Proceedings of the 14th Scandinavian Symposium and Workshops on Algorithm Theory (SWAT), pages 1-12, 2014.
D. Ajwani, N. Sitchinava. "Empirical evaluation of the parallel distribution sweeping framework on multicore architectures", in Proceedings of the 21st European Symposium on Algorithms (ESA), pages 25-36, 2013.
M. Birn, V. Osipov, P. Sanders, C. Schulz, N. Sitchinava. "Efficient parallel and external matching", in Proceedings of the 19th International Conference Euro-Par 2013 Parallel Processing (Euro-Par), pages 659-670, 2013.
L. Arge, J. Fischer, P. Sanders, N. Sitchinava. "On (dynamic) range minimum queries in external memory", in Proceedings of the 13th International Symposium on Algorithms and Data Structures (WADS), pages 37-48, 2013.
N. Sitchinava, N. Zeh, "A parallel buffer tree", in Proceedings of the 24th ACM Symposium on Parallelism in Algorithms and Architectures (SPAA) , pages 214-223, 2012.
M.T. Goodrich, N. Sitchinava, Q. Zhang, "Sorting, searching and simulation in the MapReduce framework", in Proceedings of the 22nd International Symposium on Algorithms and Computation (ISAAC), pages 374-383, 2011.
D. Ajwani, N. Sitchinava, N. Zeh, "I/O-optimal algorithms for orthogonal problems for private-cache chip multiprocessors", in Proceedings of the 26th IEEE International Parallel & Distributed Processing Symposium (IPDPS), pages 1114-1123, 2011.
D. Ajwani, N. Sitchinava, N. Zeh, "Geometric algorithms for private-cache chip multiprocessors", in Proceedings of the 18th European Symposium on Algorithms (ESA), pages 75-86, 2010.
L. Arge, M.T. Goodrich, N. Sitchinava, "Parallel external memory graph algorithms", in Proceedings of the 25th IEEE International Parallel & Distributed Processing Symposium (IPDPS), pages 1-11, 2010.
L. Arge, M.T. Goodrich, M. Nelson, N. Sitchinava, "Fundamental parallel algorithms for private-cache chip multiprocessors", in Proceedings of the 20th ACM Symposium on Parallelism in Algorithms and Architectures (SPAA), pages 197-206, 2008.
D. Eppstein, M.T. Goodrich, N. Sitchinava, "Guard placement for efficient point-in-polygon proofs", in Proceedings of the 23rd Annual ACM Symposium on Computational Geometry (SoCG), pages 27-36, 2007.
* N. Sitchinava, S. Samaranayake, R. Kapur, E. Gizdarski, F. Neuveux, T.W. Williams, "Changing scan enable during shift", in Proceedings of the 22nd IEEE VLSI Test Symposium (VTS), pages 73-78, 2004.
* S. Samaranayake, E. Gizdarski, N. Sitchinava, F. Neuveux, R. Kapur, T.W. Williams, "A reconfigurable shared scan-in architecture", in Proceedings of the 21st IEEE VLSI Test Symposium (VTS), pages 9-14, 2003.

Journal Publications

N. Sitchinava "Computational geometry in the parallel external memory model", SIGSPATIAL Special 4(2): 18-23 (2012).
* S. Samaranayake, N. Sitchinava, R. Kapur, M. Amin, T.W. Williams, "Dynamic Scan: driving down the cost of test", IEEE Computer 35(10): 63-68 (2002).

Keynote Talks

"Data Locality In High-Performance Computing", Workshop on Scientific Computing Carpentry, 2013.

Selected Invited Talks

"(Dynamic) RMQ in the External Memory and Cache-oblivious models", University of Chile, (Host: Prof. Jérémy Barbay), November 27, 2013
"Locality-conscious parallel algorithms", Georgetown University, (Host: Prof. Jeremy T. Fineman), November 14, 2013
"Locality-conscious parallel algorithms", Stony Brook University, (Host: Prof. Michael A. Bender), November 13, 2013
"PEM model and its application to GPU computing", University of Patras, (Host: Prof. Christos D. Zaroliagis), October 22, 2013
"Locality-conscious parallel algorithms", University of Ljubljana, (Host: Prof. Andrej Brodnik), October 17, 2013
"Parallel External Memory (PEM) model and its application to GPU computing", ETH Zurich, (Host: Dr. Riko Jacob), October 14, 2013
"Data locality in high-performance computing", University of Kansas, (Host: Prof. Joseph Evans), April 8, 2013
"A parallel buffer tree", TU Eindhoven, (Host: Prof. Mark de Berg), May 4, 2012
"Parallel computing — a theoretical perspective", Georgia Institute of Technology (Host: Prof. David Bader), March 17, 2011.
"Parallel computing — a theoretical perspective", Goethe University Frankfurt. (Host: Prof. Dr. Ulrich Meyer), December 20, 2010.
"Geometric algorithms for private-cache chip multiprocessors", University of California, Irvine. (Host: Prof. Michael T. Goodrich), April 30, 2010.
"Parallel external memory model for multicore architectures", Cambridge University (Host: Prof. Simon Moore), April 22, 2009.
"Parallel external memory model for multicore architectures", Dalhousie University (Host: Prof. Norbert Zeh), October 16, 2008.

Workshop Presentations

N. Sitchinava, V. Weichert. "Provably efficient GPU algorithms". Workshop on Massive Data Algorithmics (MASSIVE), 2013.
L. Arge, J. Fischer, P. Sanders, N. Sitchinava. "On (dynamic) range minimum queries in external memory". Workshop on Massive Data Algorithmics (MASSIVE), 2013.
D. Ajwani, N. Sitchinava, N. Zeh. "I/O-optimal distribution sweeping on private-cache chip multiprocessors". Workshop on Massive Data Algorithmics (MASSIVE), 2011.
D. Ajwani, N. Sitchinava, N. Zeh. "Geometric algorithms for private-cache chip multiprocessors". Workshop on Massive Data Algorithmics (MASSIVE), 2010.
L. Arge, M.T. Goodrich, N. Sitchinava. "Parallel external memory model". Workshop on Theory and Many-Cores (T&MC), 2009.
* N. Sitchinava, S. Samaranayake, R. Kapur, F. Neuveux, E. Gizdarski, T.W. Williams, "Dynamically reconfigurable shared scan-in architecture", IEEE International Test Synthesis Workshop (ITSW), 2004.
* N. Sitchinava, S. Samaranayake, R. Kapur, F. Neuveux, E. Gizdarski, T.W. Williams, D. Spielman, "A segment identification algorithms for a dynamic scan architecture", IEEE International Test Synthesis Workshop (ITSW), 2003.
* N. Sitchinava, S. Samaranayake, R. Kapur, M. Amin, T.W. Williams, "DFT - ATE solution to lower the cost of test", IEEE Workshop on Test Resource Partitioning, 2001.

Patents

Dynamically reconfigurable shared scan-in test architecture. Inventors: R. Kapur, N. Sitchinava, S. Samaranayake, E. Gizdarski, F. Neuveux, S. Duggirala, T.W. Williams. US Patents 7,900,105, 7,836,368, 7,836,367, 7,418,640, 7,596,733, 7,743,299, 7,774,663.

Last Modified: February 18, 2014