Rajesh Gupta

Rajesh Gupta (Ph. D. Stanford, M.S. UC Berkeley) is a professor in Information and Computer Science at University of California, Irvine. His research interests are in system-level design for embedded and portable systems, VLSI design, and adaptive system architectures. He also maintains an active interest in broad-band communication systems. He worked as an assistant professor at University of Illinois, Urbana-Champaign from 1994 through 1996. Prior to that he was at Intel Corporation in Santa Clara, California where he worked as a member on a number of processor design teams. He is co-author of three patents on PLL-based clock circuit; synthesis with regularity and system-on-chip modeling and a patent (filed) on data-path synthesis. He is author of a book on "Co-synthesis of Hardware and Software for Digital Embedded Systems" published by Kluwer Academic in 1995. At UCI, he leads an effort on Adaptive Memory System Architectures and co-leads an effort on Compiler-Controlled Power/Performance Management both sponsored by DARPA programs. Gupta is a recipient of the UCI Chancellor's Award for excellence in undergraduate research, National Science Foundation Career Award, two Departmental Achievement Awards and a Components Research Team Award at Intel. Gupta serves or has served as Chair of the CANDE technical committee and as a board of governor of the IEEE Circuits and Systems Society. He also serves as editor-in-chief of IEEE Design and Test and on the editorial boards of IEEE Transactions on CAD and IEEE Transactions on Mobile Computing. Gupta is a distinguished lecturer for the ACM/SIGDA and the IEEE CAS Society.

For photo click here for JPEG or here for GIF. Official vita.

Research Interests:

Patents:

  1. US 4,985,640: PLL Clock Generator Circuit
  2. US 6,148,433: Regularity Extraction for Datapath Synthesis
  3. US 6,152,612: IC/System Modeling using C++

Selected Publications:

Publications: Book

Panels, Tutorials and Short Courses

Updated July 2002.

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