DAC 1997 TUTORIAL Part I. Introduction to Embedded Cores

Table of Contents

DAC 1997 TUTORIAL Part I. Introduction to Embedded Cores

Agenda

I-1 What are core cells?Cores In Chip Design Hierarchy

One Million Transistor Chip

Available Cores

What Is A Core Cell?

Core Types

Core Types and Their Use

Core Portability

Timing Information in Firm and Hard Cores

I-2 Why core cells?Building Systems-On-A-Chip

S-O-C Application Classes

Systems-On-A-Chip (SOCs)

Component-Driven SOC

Agenda

I-3 Who are the players? CORE INDUSTRYASIC Cores Availability

FPGA/CPLD Cores Availability

Current Core Market Models

Core Trends:1997 Survey of Designers

Application Needs

Using Cores : PCI

PCI Cores

User Experience

Using Cores: DSPs

Design using DSP Cores

DSP Sample Points

Third Party DSP Cores

One-Stop Shops: LSI Logic CoreWare

Core Examples

LSI Logic: CW4001 Core

Using CW4001

CW4010 CPU Core

Advanced RISC Machines (ARM )

ARM Processor Cores

ARM Enhancements: Embedded ICE

ARM Enhancements: Thumb ISA

ARM Applications

Motorola FlexCore

Memory Core Example

Multimedia Cores

Other Core Categories

Agenda

Core-based Designs:Problem Components

Co-Design Research

Compilation & Synthesis

Compilation

Compilation & Synthesis Anatomy

Compilation for SOCs

Synthesis and Optimization

Behavioral to RTL

A Simplified Design Flow

Co-synthesis Research

1. Hardware Modeling As A Programming Activity

Hardware versus Software

HDL Semantic Necessities

HDL Pragmatics

Pragmatics (contd.)

Going from HLL to HDL

HLL Restrictions

Adding Reactivity

Adding Data Types

Embedded System Modeling

Synchronous Reactive Modeling

Example: Esterel

Language Comparisons

HDL Tools

2. Presynthesis Optimizations

Timed Decision Tables

Execution Semantics

TDT Based Control Optimization

Column Elimination Using Espresso

Pre-Synthesis Optimization Flow

TDT Optimization Results

6. A CAD Methodology for SW

6-1 Software Synthesis

Steps in Software Synthesis

Program Thread Generation

6-2. Software Optimizations

Compression

Finding Compressed Code

Locating Cache Lines

6-4. Compilation: What is New?

Machine Descriptions for Retargetability

Machine Descriptions

Machine Descriptions (contd.)

Code Generation

Putting Co-design Research Together:System Development Components

Co-Design Research Outlook

Summary of Part I

Email: gupta@uci.edu

Home Page: http://www.ics.uci.edu/~rgupta

Other information:
Copyright 1997 Rajesh Gupta Ramsey Haddad Rob Roy All rights reserved.

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