DAC 1997 TUTORIAL Part II. Design for Test of Core-Based Systems

Table of Contents

DAC 1997 TUTORIAL Part II. Design for Test of Core-Based Systems

What is Testing

Testing Core-based Systems

Difficulties in Testing CbS

System on a Chip (SOC) using Cores

Testing Responsibility of Participants

Testing Responsibility of Participants

A Typical CbS Test Strategy

Soft, Firm, and Hard Cores (based on description)

Design for Testability

Design for Testability Techniques

Scan: DFT for Sequential Circuits

Built-In Self-Test

BIST

Hard or Firm Core

Testing Hard Cores

Isolation Ring

Grid-based Direct Access

An Example of JTAG B-Scan

PPT Slide

MiniRISC CW4010 CPU Core (source: LSI Logic)

System Example: Set-Top Box Decoder

Test Methodology

IP Protection Issues

NEC’s TEST BUS

Features of NEC TESTBUS

An Example: ASIC Z

ASIC Z: Partitioning

ASIC Z: Selection

ASIC Z: Scheduling

ASIC Z: Power Analysis

ASIC Z: (Scheduling and Power)

ASIC Z: BIST Control

Debug and Diagnosis

Debug Solutions

Standardization Needs

Standardization Efforts

VSI Design Flow

VSI Data Deliverables

VSI Data Deliverables

Pattern Deliverables

VC Test Categories

Test Requirements Decision Tree

Test Requirements Decision Tree

Summary of Part II

Email: gupta@uci.edu

Home Page: http://www.ics.uci.edu/~rgupta

Other information:
Copyright 1997 Rajesh Gupta Ramsey Haddad Rob Roy Rob Roy All rights reserved.

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