A complete representation of an embedded system should include its functionality as well as its behavior over time (temporal properties). Often this functionality is specified at several levels of abstractions such as an structural connection of blocks, or in terms of its (algorithmic/RTL) behavior. Further, a system specification may contain (intentionally or inadvertently) information or directives for choices to be used in its implementation. You may start by looking at popular languages used for system specifications, particularly reactive real-time systems.
On specification of reactive systems, the following references will be useful [BL90, BW90]. Synchronous programming languages have been proposed for modeling reactive systems under the assumption that computation time is much less than communication and event interval times. A good introduction to the subject is provided by Berry in [BB91] and Esterel language is described in [Ber89]. Nicholas Halbawachs discusses use of synchronous programming using Argos in his Kluwer book [Hal93]. Specification and Description Language (SDL) [Se87, SSR89] was adopted by CCITT and has been used in the telecommunications industry, primarily for protocol specifications.
Abstract models for embedded systems broadly fall into two classes
based on their orientation towards data or control flow. There is some
debate in the community about finding a model that can be used to
efficiently perform both data and control-oriented transformation. In
addition, appropriate representation of timing behavior is needed. The
following references will provide a starting point on this
subject [CH86, HLN
90, Har92, CGH
93a, LVBA93]. Gajski in his
latest book [GVNG94] discusses use of SpecCharts as an effective
specification model which are automatically translated into VHDL code.
Transformations have been formalized and successfully applied in case of signal-processing (or data-oriented) algorithms. Parhi in [Par89] provides a good review of these techniques. Schoofs et al in [SGM94] describe signal type optimization again for DSP applications. Recent work on code optimization can be found in [Let al95]. Control transformations using control simplification and behavioral don't cares are discussed respectively in [CM94] and [Ber92a, Ber91].
Performance analysis consists of either analysis using models such as Petri Nets or others [BK90, Kob78, Sha79, Mol82]. For embedded systems, the determination of timing properties of software has been a challenging problem and is studied in by Shaw and others in [WS82, Mea89, Par92, PS90, PK89, Sha89, Sha91, YEBH93]. Recent work on this subject can be found in presentations [LM95] on software analysis (session 27) in this conference.
Constraint modeling refers to specification, capture and analysis of constraints inorder to deliver desired timing behavior or to observe bounds on resource utilization. Feasibility in time-constrained systems has often been addressed in the context of operation schedulability under given timing assumptions and processor characteristics. The following references point to literature in capturing constraints, particularly timing constraints and analysis techniques [Das85, CK86, GM94b, Lau89, Lei80, LW82, LL73].
When compiling for hardware and software from a single specification, the optimizations required use different metrics and cost criteria. The following discuss the anatomy of compilation and issues [Haa91, KW88].
Modeling,synthesis and analysis of interface between system components (particularly, hardware and software) has been a subject of research for quite some time [BK87, COB92, FKCD93, KLM93, AB91]. In recent years, the focus seems to have shifted to asynchronous hardware elements to effectively represent and synthesize interface [MD92].
The choice of a suitable architecture for hardware-software systems
is an open issue. The following publications list some of the
architectures being pursued [SS93, BRV89, CvSRM91, CGH
93b, GK89, HHW89, HHR
91, HD92, PNRK93, SB91, SBB92, Wal90].
Choice of some architectures requires a suitable division of system functionality to be implemented in either hardware or software. Work in this area is still in infancy. Some techniques are proposed in [BRX93, GM92, HK93, IOJ94, MABC92]. A survey of these techniques and partitioning based on SpecCharts are presented in [GVNG94].
Co-synthesis, that is, combined synthesis of both hardware and software
has been proposed as a viable alternative to ad hoc design methods for
embedded
systems [CGH
93b, EHB93, GM93, KL93, WWD92, RWH
93, BT93, Wol94].
Software synthesis requires not only observance of constraints on
physical memory size but also satisfaction of constraints on timing
performance. Often software generation for a given target architecture
requires linearization of operations. Such linearization may adversely
affect the satisfiability of the imposed timing constraints. How can
you determine if a valid serialization for a given set of timing
constraints exists? If so, how do you define and choose an
optimum/optimal serialization? The following references detail the
issue and point to some answers [CB94, GRVD87, GCM94, CGH
95].
Optimization of machine code for embedded systems is a more general problem than code optimization for general-purpose computing systems, due to the additional dimension of detailed timing constraints and response time requirements [Cha82, FOW87, GG90, GM94a].
Hardware synthesis from language descriptions has come a long
way in recent years due to the understanding of and advances in
behavioral and RTL synthesis techniques. Recent book by
De Micheli [Mic94] provides a good description of the
tasks and approaches for digital hardware synthesis.
The following are some pointers to the literature on the
subject [TLW
90, RWB92, CW91, MKMT90, JOI93, KM90b, KM90a, KM91, Nag79, Ber92b].
Simulation of systems containing hardware and software components presents special problem due to the need to coordinate events in two very different computation domains and yet maintain efficiency in simulations. These references point to the recent advances in this subject [BHLM91, Fis91, GCM92, tHM93, OH93, Sch90, FLLO95].
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Rajesh Gupta