References

AB91

Tod Amon and Gaetano Borriello. Sizing Synchronization Queues: A Case Study in Higher Level Synthesis. In Proceedings of the Design Automation Conference, pages 690-693, June 1991.

BB91

G. Berry and A. Benveniste. The synchronous approach to reactive and real-time systems. Another Look at Real Time Programming, Proceedings of the IEEE, 79:1270-1282, 1991.

Ber89

G. Berry. Real-time programming: General purpose or special-purpose languages. In G. Ritter, editor, Information Processing 89, pages 11-17. Elsevier Science Publishers B.V. (North Holland), 1989.

Ber91

R. A. Bergamaschi. The effect of false paths in high-level synthesis. In Proceedings of the IEEE International Conference on Computer-Aided Design, pages 80-83, 1991.

Ber92a

R. A. Bergamaschi. Control optimization in high-level synthesis using behavioral don't cares. In Proceedings of the Design Automation Conference, pages 657-661, 1992.

Ber92b

G. Berry. A hardware implementation of pure Esterel. Sadhana, Academy Proceedings in Engineering Sciences, Indian Academy of Sciences, 17(1):95-130, 1992. Also available as PRL report 15, Digital Equipment Corp., Paris Research Laboratory, 85, Av. Victor Hugo. 92563 Rueil-Malmaison Cedex, France, (1991).

BHLM91

J. Buck, S. Ha, E. A. Lee, and D. G. Messerschmitt. Ptolemy: A Platform Heterogeneous Simulation and Prototyping. In European Simulation Conference, June 1991.

BK87

G. Borriello and R. Katz. Synthesis and Optimization of Interface Transducer Logic. In Proceedings of the IEEE International Conference on Computer-Aided Design, pages 274-277, November 1987.

BK90

J. A. Bergstra and J. W. Klop. Applications of Process Algebra. In J. C. M. Baeten, editor, An introduction to process algebra, pages 1-21. Cambridge University Press, 1990.

BL90

F. C. Belz and D. C. Luckham. A new language-based approach to the rapid construction of hardware/software system prototypes. In Proc. Third International Software for Strategic Systems Conference, pages 8-9, February 1990.

BRV89

P. Bertin, D. Roncin, and J. Vuillemin. Introduction to Programmable Active Memories. In J. McCanny, J. McWhirter, and E. Swartzlander Jr., editors, Systolic Array Processors, pages 300-309. Prentice Hall, 1989.

BRX93

E. Barros, W. Rosenstiel, and X. Xiong. Hardware/Software Partitioning with UNITY. In Notes of Workshop on Hardware/Software Co-design, October 1993.

BT93

G. Berry and H. Touati. Optimized controller synthesis using esterel. In Proc. International Workshop on Logic Synthesis, Tahoe City, 1993.

BW90

A. Burns and A. Wellings. Real-Time Systems and Their Programming Languages. Addison-Wesley, 1990.

CB94

Pai Chou and Gaetano Borriello. Software scheduling in the Co-Synthesis of Reactive Real-Time Systems. In Proceedings of the Design Automation Conference, June 1994.

CGH 93a

Massimiliano Chiodo, Paolo Giusto, Harry Hsieh, Attila Jurecska, Luciano Lavagno, and Alberto Sangiovanni Vincentelli. A formal specification model for hardware/software codesign. Memorandum UCB/ERL M93/48, UC Berkeley, June 1993.

CGH 93b

Massimiliano Chiodo, Paolo Giusto, Harry Hsieh, Attila Jurecska, Luciano Lavagno, and Alberto Sangiovanni Vincentelli. Synthesis of mixed software-hardware implementations from CFSM specifications. Memorandum UCB/ERL M93/49, UC Berkeley, June 1993.

CGH 95

M. Chiodo, P. Giusto, H. Hsieh, A. Jurecska, L. Lavagno, A. Sangiovanni-Vincentelli, E. Sentovich, and K. Suzuki. Synthesis of software programs for embedded control applications. In Proceedings of the Design Automation Conference, June 1995.

CH86

P. Caspi and N. Halbwachs. A Functional Model for Describing and Reasoning Time Behavior of Computer Systems. Acta Informatica, 22(6):595-628, March 1986.

Cha82

G. J. Chaitin. Register Allocation and Spilling via Graph Coloring. SIGPLAN Notices, 17(6):201-207, 1982.

CK86

R. Camposano and A. Kunzmann. Considering Timing Constraints in Synthesis from a Behavioral Description. In Proceedings of the International Conference on Computer Design, pages 6-9, 1986.

CM94

Claudionor Coelho and G. De Micheli. Dynamic scheduling and synchronization synthesis of concurrent digital systems under system-level constraints. In Proceedings of the IEEE International Conference on Computer-Aided Design, pages 175-181, November 1994.

COB92

Pai Chou, Ross Ortega, and Gaetano Borriello. Synthesis of the Hardware/Software Interface in Microcontroller-Based Systems. In Proceedings of the IEEE International Conference on Computer-Aided Design, pages 488-495, Santa Clara, November 1992.

CvSRM91

F. Catthoor, M. van Swaaij, J. Rosseel, and Hugo De Man. Array design methodologies for real-time signal processing in the CATHEDRAL-IV synthesis environment. In Proc. Intl. Workshop on Algorithms and Parallel VLSI Architectures II, Gers, France, June 1991.

CW91

Raul Camposano and Wayne Wolf. High-level VLSI Synthesis. Kluwer Academic Publishers, 1991.

Das85

B. Dasarathy. Timing Constraints of Real-Time Systems: Constructs for Expressing Them, Method of Validating Them. IEEE Transactions on Software Engineering, SE-11(1):80-86, January 1985.

EHB93

R. Ernst, J. Henkel, and T. Benner. Hardware-Software Cosynthesis for Microcontrollers. IEEE Design & Test of Computers, pages 64-75, December 1993.

Fis91

P. A. Fishwick. Heterogeneous Decomposition and Coupling for Combined Modeling. In 1991 Winter Simulation Conference, pages 1199-1208, 1991.

FKCD93

David Filo, David Ku, Claudinor Coelho, and Giovanni De Micheli. Interface optimization for concurrent systems. IEEE Trans. VLSI Systems, September 1993.

FLLO95

Robert French, Monica Lam, Jeremy Levitt, and Kunle Olukotun. A general method for compiling event-driven simulations. In Proceedings of the Design Automation Conference, June 1995.

FOW87

J. Ferrante, K. J. Ottenstein, and J. D. Warren. The program dependence graph and its use in optimization. ACM Transactions on Programming Languages, 9(3):319-349, July 1987.

GCM92

Rajesh K. Gupta, Claudionor Coelho, and G. De Micheli. Synthesis and Simulation of Digital Systems Containing Interacting Hardware and Software Components. In Proceedings of the Design Automation Conference, pages 225-230, June 1992.

GCM94

Rajesh K. Gupta, Claudionor Coelho, and G. De Micheli. Program Implementation Schemes for Hardware-Software Systems. IEEE Computer, January 1994.

GG90

P. Gopinath and R. Gupta. Applying compiler techniques to scheduling in Real-time systems. In Proc. 1990 IEEE Real-Time Systems Symposium, pages 247-256, 1990.

GK89

J. P. Gray and T. Kean. Configurable hardware: Two case studies of micro-grain computation. In John McCanny, John McWhirter, and Earl Swartzlander Jr., editors, Systolic Array Processors, pages 310-319. Prentice Hall, 1989.

GM92

Rajesh K. Gupta and G. De Micheli. System-level Synthesis Using Re-programmable Components. In Proceedings of the European Design Automation Conference, pages 2-7, March 1992.

GM93

Rajesh K. Gupta and Giovanni De Micheli. Hardware-Software Cosynthesis for Digital Systems. IEEE Design & Test of Computers, pages 29-41, September 1993.

GM94a

Rajesh K. Gupta and Giovanni De Micheli. Constrained software generation for hardware-software systems. In Proc. Third Intl. Workshop on Hardware-Software Co-design, September 1994.

GM94b

Rajesh K. Gupta and Giovanni De Micheli. Constraint Analysis and Propagation Techniques for Embedded Systems. Tech. report, University of Illinois, 1994.

GRVD87

G. Goosens, Jan Rabaey, Joos Vanderwalle, and Hugo DeMan. An Efficient Microcode compiler for Custom DSP-Processors. In Proceedings of the IEEE International Conference on Computer-Aided Design, pages 24-27, Santa Clara, November 1987.

GVNG94

Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, and Jie Gong. Specification and Design of Embedded Systems. Prentice Hall, 1994.

Haa91

V. Haase. Real Time Behavior of Programs. IEEE Transactions on Software Engineering, SE-7(5):494-501, September 1991.

Hal93

Nicolas Halbwachs. Synchronous programming of reactive systems. Kluwer Academic Publishers, 1993.

Har92

David Harel. Biting the silver bullet. IEEE Computer, pages 8-20, January 1992.

HD92

I-J Huang and Alvin M. Despain. High Level Synthesis of Pipelined Instruction Set Processors and Back-End Compilers. In Proceedings of the Design Automation Conference, pages 135-140, June 1992.

HHR 91

R. W. Hartenstein, A. G. Hirschbiel, M. Riedmuller, K. Schmidt, and M. Weber. A novel ASIC design approach based on a new machine paradigm. IEEE Journal of Solid-State Circuits, 26(7):975-989, July 1991.

HHW89

Reiner W. Hartenstein, Alexander G. Hirschbiel, and Michael Weber. Mapping Systolic Arrays onto the Map-oriented Machine. In J. McCanny, J. McWhirter, and E. Swartzlander Jr., editors, Systolic Array Processors, pages 320-336. Prentice Hall, 1989.

HK93

Mark Horowitz and Kurt Keutzer. Hardware-Software Co-Design. In Proceedings of the Synthesis and Simulation Meeting and International Interchange, pages 5-14, 1993.

HLN 90

D. Harel, H. Lachover, A. Naamad, A. Pnueli, M. Politi, R. Sherman, A. Shtull-Trauring, and M. Trakhtenbrot. Statemate: a working environment for the development of complex reactive systems. IEEE Transactions on Software Engineering, 16(4):403-414, April 1990.

IOJ94

T. Ben Ismail, K. O'Brien, and A. Jerraya. Interactive system-level partitioning with PARTIF. In Proceedings of the European Design Automation Conference, 1994.

JOI93

Ahmed Jerraya, K. O'Brien, and T. B. Ismail. Linking system design tools and hardware design tools. In International Conference on Computer Hardware Description Languages and their Applications - CHDL'93, April 1993.

KL93

Asawaree Kalavade and Edward A. Lee. A Hardware-Software Codesign Methodology for DSP Applications. IEEE Design and Test Magazine, pages 16-28, September 1993.

KLM93

Tilman Kolks, Bill Lin, and Hugo De Man. Sizing and Verification of Communication Buffers for Communicating Processes. In Proceedings of the IEEE International Conference on Computer-Aided Design, pages 660-664, November 1993.

KM90a

D. Ku and G. De Micheli. High-level Synthesis and Optimization Strategies in Hercules and Hebe. In Proceedings of the European ASIC Conference, pages 111-120, Paris, France, May 1990.

KM90b

D. Ku and G. De Micheli. Optimal synthesis of control logic from behavioral specifications. VLSI Integration Journal, 3(10):271-298, February 1990.

KM91

David C. Ku and Giovanni De Micheli. Synthesis of ASICs with Hercules and Hebe. In Raul Camposano and Wayne Wolf, editors, High-level VLSI Synthesis, pages 177-203. Kluwer Academic Publishers, 1991.

Kob78

H. Kobayashi. Modeling and Analysis: An Introduction to System Performance Evaluation Methodology. Reading, MA: Addison-Wesley, 1978.

KW88

Kurt Keutzer and Wayne Wolf. Anatomy of a hardware compiler. Proceedings of SIGPLAN, 23(7):95-104, July 1988.

Lau89

R. Lauber. Forecasting Real-Time Behavior During Software Design Using a CASE Environment. Journal of Real-Time Systems, 1(1):61-76, June 1989.

Lei80

D. W. Leinbaugh. Guaranteed Response Times in a Hard Real-Time Environment. IEEE Trans. Software Engg., SE-6(1):85-91, 1980.

Let al95

Stan Liao and et al. Code optimization techniques for embedded dsp processors. In Proceedings of the Design Automation Conference, June 1995.

LL73

C. L. Liu and J. W. Layland. Scheduling algorithms for multiprogramming in a hard real-time environment. Journal of the ACM, 20(1):46-61, January 1973.

LM95

Y-T S. Li and Sharad Malik. Performance analysis of embedded software using implicit path enumeration. In Proceedings of the Design Automation Conference, June 1995.

LVBA93

D. C. Luckham, J. Vera, D. Bryan, and L. Augustin. Partial Ordering of Event Sets and Their Application to Prototyping Concurrent Timed Systems. Journal of Systems and Software, July 1993.

LW82

J. Leung and J. Whitehead. On the complexity of fixed-priority scheduling of periodic, real-time tasks. Performance Evaluation, 2, 1982.

MABC92

G. Menez, M. Auguin, F. Boeri, and C. Carriere. A Partitioning Algorithm for System-Level Synthesis. In Proceedings of the IEEE International Conference on Computer-Aided Design, pages 482-487, Santa Clara, November 1992.

MD92

Kenneth L. McMillan and David L. Dill. Algorithms for Interface Timing Verification. In Proceedings of the International Conference on Computer Design, pages 48-51, 1992.

Mea89

A. Mok and et. al. Evaluating Tight Execution Time Bounds of Programs by Annotations. In Proceedings of the Sixth IEEE Workshop Real-Time Operating Systems and Software, pages 74-80, May 1989.

Mic94

Giovannni De Micheli. Synthesis and Optimization of Digital Circuits. McGraw-Hill, 1994.

MKMT90

G. De Micheli, David C. Ku, Frederic Mailhot, and Thomas Truong. The Olympus Synthesis System for Digital Design. IEEE Design and Test Magazine, pages 37-53, October 1990.

Mol82

Michael K. Molloy. Performance Analysis using Stochastic Petri Nets. In IEEE Transactions on Computers, pages 913-917, September 1982.

Nag79

A. W. Nagle. Automatic Synthesis of Micro Controllers. Annual Workshop on Microprogramming, ACM SIGMICRO Newsletter, 9:112-117, 1979.

OH93

Kunle Olukotun and Rachid Helaihel. Automating architectural exploration with a fast simulator. In Notes of the Workshop on Hardware-Software Co-design, 1993.

Par89

Keshab K. Parhi. Algorithm Transform Techniques for Concurrent Processors. In Proceedings of the IEEE, pages 1879-1895, December 1989.

Par92

C. Y. Park. Predicting deterministic execution times of Real-time Programs. PhD thesis, University of Washington, Seattle, August 1992.

PK89

P. Puschner and Ch. Koza. Calculating the maximum execution times of real-time programs. J. Real-Time Systems, 1:159-194, April 1989.

PNRK93

P. Pfahler, C. Nagel, F.-J. Rammig, and U. Kastens. Design of a VLIW architecture constructed from standard RISC chips: a case study of hardware/software codesign. In Proceedings of 19th EUROMICRO Symposium, pages 6-9, September 1993.

PS90

C. Y. Park and Alan C. Shaw. Experiments with a Program Timing Tool Based on Source-Level Timing Schema. In Proceedings of the IEEE Real-Time Systems Symposium, pages 72-81, December 1990.

RWB92

editor R. W. Broderson. Anatomy of a Silicon Compiler. Kluwer, 1992.

RWH 93

R. Roth, J. Watkins, M. Hsieh, W. Radke, D. Hejna, R. Tom, and B. Kim. An Integrated Environment for Concurrent Development of a Pixel Processor ASIC and Application Software. In Proceedings of the International Conference on Computer Design, pages 116-125, 1993.

SB91

M. B. Srivastava and R. W. Broderson. Rapid-Prototyping of Hardware and Software in a Unified Framework. In Proceedings of the IEEE International Conference on Computer-Aided Design, pages 152-155, Santa Clara, 1991.

SBB92

M. B. Srivastava, T. I. Blumenau, and R. W. Broderson. Design and implementation of a robot control system using a unified hardware-software rapid-prototyping framework. In Proceedings of the International Conference on Computer Design, 1992.

Sch90

H. D. Schwetman. Introduction to process-oriented simulation and csim. In Proc. Winter Simulation Conference, New Orleans, LA, December 1990.

Se87

R. Saracco and P. A. Tilanus (editors). SDL'87: State of teh Art and Future Trends. North-Holland, 1987.

SGM94

K. Schoofs, G. Goossens, and H. De Man. Signal Type Optimisation in the design of time-multiplexed DSP architectures. In Proceedings of the European Design Automation Conference, March 1994.

Sha79

S. D. Shapiro. A stochastic Petri net with applications to modeling occupancy times for concurrent task systems. Networks, 9:375-379, 1979.

Sha89

A. Shaw. Reasoning about Time in Higher Level Language Software. IEEE Trans. Software Engg., 15(7):875-889, July 1989.

Sha91

A. C. Shaw. Deterministic Timing Schema for Parallel Programs. In Proc. 5th Intl. Parallel Processing Symposium, pages 56-63, 1991.

SS93

A. Smailagic and D. P. Siewiorek. A case study in embedded system design: the VuMan 2 wearable computer. IEEE Design & Test of Computers, pages 56-67, September 1993.

SSR89

Roberto Saracco, J. R. W. Smith, and Rick Reed. Telecommunications systems engineering using SDL. North-Holland, 1989.

tHM93

K. ten Hagen and H. Meyr. Timed and untimed hardware/software co-simulation: Application and efficient implementation. In Internation workshop on hardware-software codesign, 1993.

TLW 90

D. Thomas, E. Lagnese, R. Walker, J. Nestor, J. Rajan, and R. Blackburn. Algorithmic and Register-Transfer Level: The System Architect's Workbench. Kluwer Academic Publishers, 1990.

Wal90

S. Walters. Reprogrammable hardware emulation automates system-level ASIC validation. In WESCON/90 Conference Record, pages 650-653, Anaheim, California, November 1990.

Wol94

Wayne Wolf. Hardware-Software Co-design of Embedded Systems. IEEE Proceedings, 82(7):965-989, July 1994.

WS82

Martin C. Wei and Howard A. Sholl. An Expression Model for Extraction and Evaluation of Parallelism in Control Structures. IEEE Transactions on Computers, C-31(9), September 1982.

WWD92

Nam Woo, Wayne Wolf, and Al Dunlop. Compilation of a single specification into hardware and software. In International Workshop on Hardware-Software Co-design, October 1992.

YEBH93

W. Ye, R. Ernst, Th. Benner, and J. Henkel. Fast timing analysis for hardware-software co-synthesis. In Proceedings of the International Conference on Computer Design, 1993.