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1. Physical Design 2. Logic-level Synthesis and Verification 3. Testing, Design for Testability 4. Design and Tools for Low Power 5. Architectural-level Synthesis 6. Embedded System Hardware/Software Co-Design |
7. Embedded Software, Code Generation 8. Field Programmable Gate Arrays 9. Multichip Modules 10. Specialized VLSI Architectures 11. Deep Sub-micron VLSI Design 12. Applications |
Professor Farid Najm, GLS-VLSI'97 209 C&SRL University of Illinois 1308 W. Main Urbana, Illinois 61801. Email: najm@uiuc.edu Tel: (217) 333-7678 Fax: (217) 244-1946
| Chair | Naveed Sherwani, Intel Corporation. | sherwani@ichips.intel.com |
| General Co-chair | Steve (Sung-Mo) Kang | kang@uivlsisg.csl.uiuc.edu |
| General Co-chair | C. L. Liu | liucl@cs.uiuc.edu |
| Technical Program Chair | Farid Najm | najm@csl.uiuc.edu | Local Arrangements | Naresh Shanbhag | shanbhag@uivlsi.csl.uiuc.edu | Publicity Chair | Rajesh Gupta | rgupta@cs.uiuc.edu |
Visitor Count: since May 23, 1996.
rgupta@cs.uiuc.edu