Integrated Embedded Systems Automation Group: Talks

Important Notice:

This on-line material is being provided in the interest of rapid dissemination of information related to the research work conducted by the IESAG group. Some or all of the material here may be covered by copyright owned by the respective authors. You may browse the material at your convenience as you would in a public library. Permission is also granted to make a hard copy for personal use without fee provided that the copied material clearly indicates the author and source of the material and any original copyright notations are unaltered on every portion of the referenced material. Retrieval, copy, or distribution of any material herein for profit or any commerical advantage may violate the copyright protection law and requires prior written permission of the copyright owners.

Online Strategies for Power/Performance Management in Embedded Systems

Qualcomm, Nov, 2002

Abstract
Effective management of energy and power in microsystems requires active participation of all the actors from applications to system
software to network interfaces in making the right power/performance/quality choices. In this talk, I will describe results from our
ongoing work on characterization of effectiveness of the power management algorithms and a software architecture that enables the
application developer to turn the right hardware and subsystem "knobs" based on application context and dynamically changing
performance/quality requirements.

Slides

UCI Mobile Computing Testbed

Ongoing projects. Slides.

Structured Composition Techniques for Embedded Systems

Presentation at HiPC02, December 2002.

 

Power Aware Software Architecture

Presentation at JPL-CASS Workshop, September 2002

 

Dynamic Power Management for Systems with Multiple Power Saving States

Presentation at DATE 2002, March 2002

Profile Based Dynamic Voltage Scheduling with Program Checkpoints


Presentation at DATE 2002, March 2002

Power Savings in Embedded Processors with Decode Filter Cache


Presentation at DATE 2002, March 2002

Interfaces and Software Layer

Presentation to Cal-IT2 Advisory Board, 2/8/02

Application-Adaptive Architectures -- The AMRM Project

Tensilica Inc., Feb 22, 1999

Abstract

Continuing trends in microelectronic technology are beginning to fundamentally alter the ground rules in the design of high performance circuit blocks and the role of interconnect between the circuit blocks. Our research group is particularly interested in understanding the impact of these technology trends for on-chip system architecture and design tools for the coming generations of process technologies.

This talk presents the case for adaptivity in system architectures -- from single-chip embeddable processor cores to multiprocessor systems -- that relies on application-driven hardware customization to achieve cost-effective system implementations. Architectural customization, achieved using synthesizable logic blocks and computer-aided design tools, is used to improve system performance while keeping system development and product costs down. We describe highlights from the on-going research activity on the Adaptive Memory Reconfiguration Management (AMRM) project that uses architectural adaptation to improve the performance of memory subsystem and communication resources.

This talk describes on-going research activity. We welcome participation and feedback from the audience. Further details and related publication pointers can be found at http://www.ics.uci.edu/~amrm.

Slides

Design Technology and Architectural Adaptation for Deep Sub-micron VLSI Systems

June 4, 1998: University of California, Los Angeles

Abstract

We present an assessment of the technology trends and its implications for the computer systems architecture and design tools for the coming generations of process technologies. Based on technology projections from the SIA road-map, the cumulative effect of continuing increases in interconnect delay relative to gate switching would fundamentally alter the ground rules in the design of high performance circuit blocks and the role of interconnect between the circuit blocks. For instance, multiple storage elements could be located in a cycle period whereas block-level interconnect would no longer be a part of the cycle time. Architecturally, increased local decision making can be used to adapt a data-path to application-specific computational requirements. To illustrate how this adaptability can be used in efficient system architectures, we present highlights from the study of latency-hiding mechanisms to improve the interaction of processing and memory elements as a part of the on-going DARPA-sponsored project on high-performance data-intensive embedded computing.

From a design technology standpoint, language-level modeling and system co-design of hardware/software blocks under strict timing constraints present a special challenge to the next generation of system design tools. The new design technology must balance increasing technology dependence while advancing the level of abstraction towards target applications. I will present an overview of our work system-level CAD algorithms and describe how system design problems are addressed in a framework that allows the system architect to interactively explore intelligent design options without leaving the application development environment. This talk describes on-going research activity. We welcome participation and feedback from the audience.

Slides

Co-design Tools for Architecting Systems-On-A-Chip

December 1, 1997: Rockwell International

Abstract

Recent availability of cores, or pre-designed specialized function cells such as microprocessors, RF components, network interfaces, encryption and compression engines, has lead to exciting possibilities in building complex systems on a single-chip for embedded systems in a short time. Computing elements in these systems can be used to deliver application functionality, build and manage mobility, improve system performance, improve testability and reliability of these systems by adapting to application needs. A good system design, especially for single-chip implementations, requires effective integration of system digital and mixed-signal hardware, and software components. To handle system complexity, novel architectural approaches and system integration tools are needed to ensure that the system integration is correct, robust and manufacturing viable against the technology challenges and process variations and poor device characteristics particularly for analog and RF applications. In this talk, we will identify the bottlenecks in system co-design from specification to system partitioning and co-simulation challenges.

This talk presents an overview of the on-going research on design tools for single-chip embedded computing systems for moderately complex computing and non-computing applications such as network interfaces and broadband switching at University of California, Irvine. We describe how system design problems are addressed in a CAD framework that allows the system architect to interactively explore intelligent design options without leaving the application development environment.

Relevant Publications

Slides

Tutorial on Design Tools for Wireless Systems

International Conference on Computer Aided Design, November, 1997.

Click here to begin.

Rate Constraint Debugging In Embedded Systems using Fast Maximum Mean Cycle Algorithms

May 20, 1997: University of California, Los Angeles.

Abstract:

A rate constraint on an operation specifies an upper or lower bound the rate of execution of the operation. In many performance critical embedded systems, rate constraints specify the throughput and response requirements on systems that are in continuous interaction with their environment. In case of a constraint violation, constraint "debugging" is needed to localize the source of constraint violation. The high complexity of these problems entails a systematic and automated framework to help the designer in producing correct system implementations in a short design time. In this talk, I will describe such a framework and its use in an interactive design environment. Constraint analysis is driven by a two-phase rate analysis algorithm that builds upon detection of maximum mean cycles in process graphs. I will describe a novel algorithm for solving maximum (and minimum) mean cycle problems that uses implicit process "unfolding" to improve upon the fastest known maximum mean cycle algorithms. Both asymptotic analysis and experimental results confirm the effectiveness of the new algorithm. We demonstrate by examples how the proposed rate analysis can be used in system design.

Slides

Tutorial on Core-based System Design

Click here to begin.

Important Notice:

This on-line material is being provided in the interest of rapid dissemination of information related to the research work conducted by the IESAG group. Some or all of the material here may be covered by copyright owned by the respective authors. You may browse the material at your convenience as you would in a public library. Permission is also granted to make a hard copy for personal use without fee provided that the copied material clearly indicates the author and source of the material and any original copyright notations are unaltered on every portion of the referenced material. Retrieval, copy, or distribution of any material herein for profit or any commerical advantage may violate the copyright protection law and requires prior written permission of the copyright owners.
rgupta@ics.uci.edu