Hardware-Software Co-design:Tools for Architecting Systems-On-A-Chip

12/3/97

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Table of Contents Hardware-Software Co-design:Tools for Architecting Systems-On-A-Chip A System Architecture: Today A System Architecture: Tomorrow Embedded Computing EC Application Classes Outline Co-Design Problem Areas Applying Co-Design Co-Design Problems Co-synthesis Embedded Computing Systems 1. Timing Constraints Analysis Example A Two-level System Model for Rate Analysis Rate Analysis at Operation Level Rate Analysis at Process Level Critical Cycles Rate of Process Executionfor Single SCC Rate Analysis on Process Graphs with Multiple SCCs Interactive Analysis Framework[Dasdan, Mathur, Gupta, EDTC’97] Constraint Consistency Analysis Steps 2. Design Modeling:Semantic Necessities Adding Reactivity Pragmatics Using C++ For Synthesis and Simulation Scenic Concepts Wait() and Watching() Methodological Issues: Synthesis Going from C++ to HDL Adding Reactivity Example: W & W Adding Data Types Language Comparisons 3. The Problem in Architectural Validations What is Great About DES Models? What is wrong with DES Models Programmed in HLLs? System Simulations Our Approach Program-Driven System Simulation Examples Simulation Workbench Prefetching Experiments Experimental Results: Simulation Speed Co-design Outlook Summary Summary Pointers

Author: ICS Email: gupta@uci.edu Home Page: http://www.ics.uci.edu/~rgupta Other information: All rights reserved.