About Me

I'm a PhD Candidate of Department of Computer Science at UC Irvine. I started my study at 2008 after I had worked for Samsung Electronics as a System-on-Chip designer for more than 10 years, just because I want to challenge another life in USA. Although I had to give up my stabilized life in Korea, I've never regretted of my choice. I could make lots of friends, I could make fantastic experience at Southern California, and I could study!

Challenge your life!

Advisor: Prof. Alexander V. Veidenbaum

Contacts

• Email: tkim15 [at] ics [dot] uci [dot] edu
• Email: tkim15 [at] uci [dot] edu
• Office: DBH3068, UCI Main Campus

Education

• PhD Candidate, Computer Science, University of California, Irvine, USA, 2008 ~ 2013 (expected) (GPA: 3.80)
• MS, Electrical Engineering, Kyungpook National University, South Korea, 1996 (GPA: 3.75)
• BS, Electrical Engineering, Kyungpook National University, South Korea, 1994 (GPA: 3.56)

Research Interests

Although I'm interested in a lot of areas, currently, I'm concentrating on Computer Architecture and Embedded Systems.

• Computer Architecture: Prefetcher, Memory Hierarchy, High-Performance Computing, Multi-Core System
• Embedded Systems: System Architecture, System Security

Publications

Dissertation

• Taesu Kim, Modeling Multi-Sensor Signal Processor using VHDL, Kyungpook National Univ., 1996

Patents

• KS 10-0564610-0000 (03/21/2006) "Demultiplexer and demultiplexing method of the digital broadcasting receiver capable of demultiplexing several broadcasting channel signals"
• KS 10-0546371-0000 (01/19/2006) "Multiple multimedia data receiving and saving apparatus including transport stream demultiplexing unit and conditional access/content protection unit"
• KS 10-0498447-0000 (06/22/2005) "Composite FFT calculating apparatus, method and recording media"
• KS 10-0486307-0000 (04/21/2005) "Apparatus for calculating an Observation Probability of Hidden Markov model algorithm"
• KS 10-0464428-0000 (12/22/2004) "Apparatus for recognizing a voice"
• US 20040002862 (01/01/2004) "Voice recognition device, observation probability calculating device, complex Fast Fourier Transform calculation device and method, cache device, and method of controlling the cache device"
• KS 10-0338773-0000 (05/18/2002) "State-metric operating apparatus for reducing power of Viterbi decoder"

Industry Experience

• Samsung Electronics Co., Ltd. System LSI Division, 2001 ~ 2008, Senior Engineer
• Samsung Advanced Institute of Technology, 1996 ~ 2001, Researcher

Projects

At SEC,

• Multi-Format Encoder/Decoder (MFC) Design (2007 ~ 2008)
• - Technical Leader for decoder part.
• - Architect, Verilog-RTL Coding/Simulation, Logic Synthesis, Static Timing Analysis, Equivalence Check
• - Decoder H.264, MPEG-2 Video, MPEG-4/Divx, H.263.
• - Encoder H.264, MPEG-2 Video, H.263.
• - OpenRISC, 250 MHz @65nm, 3 MGates
• Multi-Format Decoder (MFD) Design (2005 ~ 2007)
• - Technical Leader.
• - Architect, Verilog-RTL Coding/Simulation, Logic Synthesis, Static Timing Analysis, Equivalence Check
• - Implementation of H.264, MPEG-2 Video, MPEG-4/Divx, H.263.
• - OpenRISC, 220 MHz @65nm, 2 MGates
• - Product: A1 (Dual ARM11 core, 30 MGates, @65nm)
• CableCARD Processor Design (2004 ~ 2005)
• - Project Leader.
• - Architect, Verilog-RTL Coding/Simulation, Logic Synthesis, Static Timing Analysis, Equivalence Check
• - Conditional Access System Module for Cable Set-top-Box.
• - Implementation of ANSI/SCTE 28 HOST-POD Interface Standard.
• - Supports Conditional Access System (CAS): DVB-CSA, NDS ICAM® and SmartCard (ISO 7816).
• - ARM940T, 150 MHz, @130nm, 2 MGates
• - Product: S5H2500
• Transport Stream Demultiplexer (TSD) Design (2003 ~ 2006)
• - Technical Leader.
• - Architect, Verilog-RTL Coding/Simulation, Logic Synthesis, Static Timing Analysis, Equivalence Check
• - Digital TV Broadcasting Stream (Transport Stream) receiver.
• - Implementation of MPEG-2 Part 1 System (ISO/IEC 13818-1).
• - Supports ATSC (A/53 Part-3), DVB and DIRECTV.
• - Supports Conditional Access System (CAS): NRSS (EIA-679-B), DVB-CI (EN 50221), DES, TDES, DVB-CSA, AES, NDS ICAM® and SmartCard (ISO 7816).
• - ARM7TDMI, 60~90 MHz @90nm, 900 kGates
• - Products: S5H2200, S5H2201, S5H2110, S5H2111, S5H2112

At SAIT,

• Human Computer Interface (HCI) Processor Design (2001 ~ 2003)
• - Project Leader.
• - Architect, Verilog-RTL Coding/Simulation, Logic Synthesis, Static Timing Analysis
• - ARM920T based System-on-Chip (SoC).
• - Implemented specialized module for Speech Recognition, Speech Codec, Face Recognition and Text-to-Speech.
• - Sample chip was tested on demo board.
• Speech Recognition Application Specific DSP Design (2000 ~ 2001)
• - Researcher
• - VHDL RTL Coding/Simulation
• - Speech Recognition of 50 isolated words.
• - Designed from ISA to Sample ASIC.
• - Sample chip was tested on demo board (Television Remote Controller).
• Ultrasound Medical System Design (1997 ~ 1998)
• - Researcher
• - Blood speed measurement using Doppler Effect.
• - Modeling and simulation were done by Cadence SPW.
• - Prototype board was made and tested.

Tools

For Logic Design,

• Synopsys, Inc.: DC Ultra, Power Compiler, DFT MAX, DesignWare IP, Formality, PrimeTime, Identify Pro
• Cadence Design Systems, Inc.: Incisive Simulator, Conformal Equivalence Checker
• Mentor Graphics: ModelSim
• SpringSoft, Inc.: Verdi
• Atrenta Inc.: SpyGlass

For FPGA Validation,

• Synplicity, Inc: Synplify Pro, Identify
• Xilinx, Inc: ISE Design Suite

For Programming,

• C, C-Shell script, Shell script
• ClearCase, CVS, SubVersion, Awk, Sed, Perl

References

• Prof. Pyung Choi, Kyungpook National University, South Korea
• Email: p0choi [at] ee [dot] knu [dot] ac [dot] kr
• Associate Prof. Jongwoo Bae, Myongji University, South Korea
• Email: jwbae [at] myu [dot] ac [dot] kr
• Associate Prof. Jinsoo Cho, Kyungwon University, South Korea
• Email: jscho [at] kyungwon [dot] ac [dot] kr

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