Logic
This describes a design by logic gates and the connections between them. For example: 2 to1 multiplexor is a kind of building module of RTL:
Figure 1. Overview of 2 to 1 Multiplexor
Figure 1 means the 2 to 1 multiplexor operates as: when select=”0”, out = in0; when select = “1”, out = in1. Using Verilog HDL to describe this behavior as:
module multiplexor2to1 (out,in0,in1,select);
output out;
input in0,in1,select;
reg out;
always @(in0 or in1 or select)
case(select)
1’b0:out=in0;
1’b1:out=in1;
default:$display(“Please check select bit”);
endcase
endmodule
At Logic-level, it can be implemented using gates:
Figure 2. Using gate implements 2 to 1 Multiplexor
And also can use Verilog HDL to describe the above implementation:
module nand(out, in1, in2);
output out;
input in1, in2;
assign out = ~(in1&in2);
endmodule
module not(out, in);
output out;
input in;
assign out = ~ in;
endmodule
module multiplexor2to1 (out, in0, in1, select);
output out;
input in0,in1,select;
not g1(select_bar, select);
nand g2(out_g2, in0, select_bar);
nand g3(out_g3, in1, select);
nand g4(out,out_g2,out_g3);
endmodule
1. Open source resources
A free download and open source code logic developing tool:
http://www.staticfreesoft.com/productsFree.html
2. Web pages
A good course notes from Stanford EE275:
http://www.stanford.edu/class/ee275/
3.Citations