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| Instructor: |
Ian G. Harris |
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| Goals: |
Design of computer elements: ALU, control unit, and arithmetic
circuits. Memory hierarchy and organization. Caches. Function unit
sharing and pipelining. I/O and interrupt processing. RTL and
behavioral modeling using hardware description
languages. Microprocessor organization and implementation techniques.
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| Book: |
David A. Patterson and John
L. Hennessy, Computer Organization and Design: The
Hardware/Software Interface , Third Edition, 2004
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| Requirements: |
- Problem Sets: 30%
- Quizzes: 45%
- Final: 25%
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| Assignments: |
The course will have four problem sets and four quizzes. The quiz and
problem set with the lowest grade will be dropped from consideration
in your final grade. The problem sets will be posted on the website at
least 7 days before they are due. Problem set solutions will be posted
on the web site the same day they are due, so no late problem sets
will be accepted. Quiz dates will be posted on the web site at least
10 days in advance of the quiz date. Quizzes will be conducted in
class.
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| Course Location: |
MWF 9:00-10:50, HIB 100
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| Office Hours: |
MW 11:00-12:00, CS 408D |
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| Prerequisites: |
ICS 151 |
| Cheating: |
Violation of the UCI dishonesty policy will be punished with a grade of F in the class. |
| Problem Sets/Quizzes: |
Due Dates and Quiz Schedule |
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| Syllabus: |
- Instruction Sets
- Instruction Formats
- Logical/Arithmetic Operations
- Load/Store Operations
- Control Operations
- Addressing Modes
- Computer Arithmetic
- Number Representations
- Addition/ Subtraction/ Multiplication
- Floating Point Arithmetic
- Performance Measurement
- Throughput, Response Time
- Clock Rate, CPI
- SPEC Benchmarks
- Datapath and Control
- Building datapath/control from instructions
- RTL Components
- Multicycle Instructions
- Control State Machines
- Exceptions
- Pipelining
- Pipeline Execution and Design
- Data, Control Hazards
- Pipelined Datapaths and Control
- Forwarding and Stalls
- Branch Hazards
- Memory Hierarchy
Caches
- Cache Performance
- Associativity in Caches
- Virtual Memory
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