References

Optimizing subroutines in assembly language. An optimization guide for x86 platform. by Agner Fog. Instruction tables: Lists of instruction latencies, throughputs and micro-operation breakdowns for Intel, AMD and VIA CPUs by Agner Fog. Software optimization resources from Agner Fog.

Cache Coherence Protocol and Memory Performance of the Intel Haswell-EP Architecture. link

Intel SGX Explained pdf

Security evaluation of Intel's active management technology. Vassilios Ververis, 2010.

DC Express: Shortest Latency Protocol for Reading Phase Change Memory over PCI Express pdf

Updated: January, 2019