HW1: RISC instruction set, pipelining

Note: Make reasonable assumptions where necessary and clearly state them. Feel free to discuss problems with classmates, but the only written material that you may consult while writing your solutions are the textbook, lecture notes, and lecture slides.

Problem 1: RISC Instruction set

Take a look at the RISC instruction set in the book (Section A.9). Write a simple RISC assembly program that finds a sum of even numbers from 1 to N (you can assume that N is in one of the registers when you program starts)

Problem 2: Basic pipelining

An unpipelined processor takes 3 ns to work on one instruction. It then takes 0.2 ns to latch its results into latches. I was able to convert the circuits into 6 equal sequential pipeline stages. Answer the following, assuming that there are no stalls in the pipeline.

  • What are the cycle times in the two processors?
  • What are the clock speeds?
  • What are the IPCs?
  • How long does it take to finish one instruction?
  • What is the speedup from pipelining?
  • If I was able to build a magical 1000-stage pipeline, where each stage took an equal amount of time, what speedup would I get?

Problem 3: Data Dependencies

Show how the following four consecutive instructions move through each stage of the five stage pipeline that we discussed in class. This pipeline does not support any bypassing. Make sure the decode stage does not advance an instruction through the pipeline unless all data dependences are correctly resolved.
    I1: add r1, r2, r3
    I2: lw r4, 4(r4)
    I3: add r5, r4, r1
    I4: sw r5, 8(r2)
Show how the same four instructions move through each stage of the five stage pipeline, but now assume that the pipeline does support bypassing. Make sure the decode stage does not advance an instruction through the pipeline unless all data dependences are correctly resolved.
    I1: add r1, r2, r3
    I2: lw r4, 4(r4)
    I3: add r5, r4, r1
    I4: sw r5, 8(r2)

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Updated: November, 2019