Description

This invited workshop aims to bring together researchers and designers from academia and industry to discuss directions in the development of high-performance, parallel, distributed, and multimedia processors and systems. The workshop invitees are computer architects and compiler, operating system, and application experts. The main goal of the workshop is to discuss future trends in the development of architecture and software systems and to explore the assumptions made by the architects about software systems and by software writers about architecture. The increased complexity in each of these areas calls for increased interaction with researchers from all of the other disciplines to accurately assess the potential directions and future trends in architecture and systems.

The main themes of the workshop are software- and technology-driven and constrained new architectures, compiler/architecture interaction and codesign, and application requirements and characteristics. Both numerical and non-numerical applications, such as database, data mining, Web- and Java-based, and (high-performance) embedded applications, are of interest. In all cases a longer-term view and assessment of the future is of most interest.

This year's special focus is power-aware memory hierarchy. Today both high-performance and embedded processors and systems are concerned with power dissipation. Memory hierarchy is one of the major sources of on-chip and system power consumption. Until recently this concern was primarily addressed via technology and circuit design. An important and interesting issue is whether (micro)architectural innovation and compiler support can make significant contributions to reducing the power dissipation. Workshop topics of interest will deal with this issue and include but are not limited to:

• Cache organizations that reduce power consumption
• Use of adaptive techniques in the hierarchy to reduce power consumption
• Power-performance trade-offs in the memory hierarchy
• Compiler techniques to manage the hierarchy to reduce power consumption
• Modeling, benchmarking, performance and power consumption evaluation
• Other microarchtecture and compiler techniques for reducing power consumption

Additional workshop areas of interest include the perennial favorites below, but preference will be given to submissions on the above-mentioned topics.

• Processor design
  
• Single-chip multiprocessors, multi-chip servers and large-scale multiprocessors
  
• Memory technology and system organization
  
• Systems On a Chip (SOC)
  
• Architecture-compiler interaction and optimization
  
• Applications and there performance

The workshop will consist of sessions combining individual presentations with discussion. Presentations will be limited to ~20 min to provide sufficient time for discussion. An ideal presentation will concentrate on trends and future directions in addition to recently obtained results. Speculation is encouraged.

Workshop participation is capped at 25 invitees.

The invitees wishing to make a presentation should submit an extended abstract, up to 3 pages, by 1/6/01. Submissions should be electronic in postscript or pdf format. The abstracts will be reviewed and printed in the on-site proceedigns.

The final proceedings consisting of full papers will be published by IEEE Computer Society Press after the meeting. The papers will undergo an additional review process and be selected for publication in the post-proceedings. Papers will be due by ~April 1st 2001.
The following set of LaTex macros should be used in preparing the final paper. Additional publication instructions will be made available at a later date.

Participants