International Workshop on Innovative Architecture for Future
Generation High-Performance Processors and Systems

Date: January 12-13, 2004
Place: Maui, Hawaii
Location: Maui Prince hotel

Sponsored by Maui High Performance Computing Center
Center for Embedded Computer Systems, UC Irvine

Program Committee

Prof. Hideharu Amano Keio U
Prof. Takanobu Baba Utsunomiya U
Prof. Kei Hiraki U Tokyo
Prof. Kazuki Joe Nawa Women's U
Prof. Peter Kogge, Notre Dame
Prof. Trevor Mudge, Michigan
Prof. Alex Orailoglu, UCSD
Prof. Isaac Scherson, UC Irvine
Prof. Hironori Kasahara Waseda U
Prof. Masaru Kitsuregawa U Tokyo
Prof. Hironori Nakajo TUAT
Prof. Hiroshi Nakashima TUTICS
Prof. Shuichi Sakai U Tokyo
Prof. Mateo Valero, UPC Spain
Prof. Alex Veidenbaum, UC Irvine

Local Arrangements Chair: TBD
Finance Chairs: Profs. Nicolau and Joe
Publication Chair: Prof. Veidenbaum

Workshop description
Submission
Participants
Local Arrangements
Preliminary Program

IWIA Steering Committee


Description

This invited workshop aims to bring together researchers and designers from academia and industry to discuss directions in the development of high-performance, parallel, distributed, and multimedia processors and systems. The workshop invitees are computer architects and compiler, operating system, and application experts. The main goal of the workshop is to discuss future trends in the development of architecture and software systems and to explore the assumptions made by the architects about software systems and by software writers about architecture. The increased complexity in each of these areas calls for increased interaction with researchers from all of the other disciplines to accurately assess the potential directions and future trends in architecture and systems.

The main themes of the workshop are software- and technology-driven and constrained new architectures, compiler/architecture interaction and co-design, and application requirements and characteristics. Both numerical and non-numerical applications, such as database, data mining, Web- and Java-based, and (high-performance) embedded applications, are of interest. In all cases a longer-term view and assessment of the future is of most interest.

This year's special focus is custom vs general-purpose processors and systems. Today's processors are increasingly specialized. Significant performance, cost, power, and ease/quality of programming can be achieved if application area requirements and constraints are taken advantage of. Design, compilation, power management, application area requirements, performance evaluation of such processors and systems and their comparison with general-purpose systems are some of the workshop topics.

Other topics of interest include but are not limited to the following:

The workshop will consist of sessions combining individual presentations with discussion. Presentations will be limited to ~20 min to provide sufficient time for discussion. An ideal presentation will concentrate on trends and future directions in addition to recently obtained results. Speculation is encouraged.

Workshop participation is capped at 25 invitees.

Submission and Publication

The invitees wishing to make a presentation should submit an extended abstract, up to 3 pages, by 1/3/04. Submissions should be electronic in postscript or pdf format. The abstracts will be reviewed and printed in the on-site proceedigns.

The final proceedings consisting of full papers will be published by IEEE Computer Society Press after the meeting. The papers will undergo an additional review process and be selected for publication in the post-proceedings. Papers will be due by ~April 1st 2004.
The following set of LaTex macros should be used in preparing the final paper. Additional publication instructions will be made available at a later date.

Participants

USA

To be announced

To be announced