International Workshop on Innovative Architecture for Future
Generation High-Performance Processors and Systems

Date: January 11-13, 2007
Meeting Location: Maui High Performance Computing Center
Conference hotel: Maui Prince Hotel


Program Committee

Prof. Gianfranco Bilardi, U of Padua Italy
Prof. Mario Furnari, ICIB-CNR Italy
Prof. Kyle Gallivan, Florida State
Dr. William Gropp, Argonne Natl. Lab
Prof. Kenji Kise, Tokyo Tech Japan
Prof. Atsushi Kubota, Hiroshima City U Japan
Prof. Satoshi Matsuoka, Tokyo Tech Japan
Prof. Hiroshi Nakamura, U of Tokyo Japan
Prof. Hironori Nakajo, TUAT Japan
Prof. Alex Orailoglu, UCSD
Prof. Elefterios Polychronopoulos, U of Patras Greece
Prof. Toshinori Sato, Kyushu U Japan
Prof. Guri Sohi, Wisconsin
Prof. Kiyofumi Tanaka, JAIST Japan
Prof. Tsutomu Yoshinaga, UEC Japan

Local Arrangements Chair: Alex Veidenbaum
Finance Chairs: Profs. Nicolau and Joe
Publication Chair: Prof. Nakajo

Workshop description
Submission
Participants
Local Arrangements
Preliminary Program

IWIA Steering Committee


Description

This invited workshop aims to bring together researchers and designers from academia and industry to discuss directions in the development of high-performance, parallel, distributed, and multimedia processors and systems. The workshop invitees are computer architects and compiler, operating system, and application experts. The main goal of the workshop is to discuss future trends in the development of architecture and software systems and to explore the assumptions made by the architects about software systems and by software writers about architecture. The increased complexity in each of these areas calls for increased interaction with researchers from all of the other disciplines to accurately assess the potential directions and future trends in architecture and systems.

The main themes of the workshop are software- and technology-driven and constrained new architectures, compiler/architecture interaction and co-design, and application requirements and characteristics. Both numerical and non-numerical applications, such as database, data mining, Web- and Java-based, and (high-performance) embedded applications, are of interest. In all cases a longer-term view and assessment of the future is of most interest.

This year's special focus is on multi-core systems and hierarchical systems and ways to explore single-program parallelism on such systems. All aspects of design, compilation, and application design are of interest for both single-chip multi-core processors and multi-processor systems built from such chips and are the 2007 special topics.

Other topics of interest include but are not limited to the following:

The workshop will consist of sessions combining individual presentations with discussion. Presentations will be limited to ~20 min to provide sufficient time for discussion. An ideal presentation will concentrate on trends and future directions in addition to recently obtained results. Speculation is encouraged.

Workshop participation is capped at 25 invitees.

Submission and Publication

The invitees wishing to make a presentation should submit an extended abstract, up to 3 pages, by 1/6/07. Submissions should be electronic in pdf format. The abstracts will be reviewed and printed in the on-site proceedigns.

The final proceedings consisting of full papers will be published by IEEE Computer Society Press after the meeting. The papers will undergo an additional review process and will be selected for publication in the post-proceedings. Papers will be due by July 1st 2007.
Publication instructions will be distributed by CS Press at a later date.

Participants

USA

To be announced

To be announced